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-rw-r--r--src/arch/arm/isa/insts/sve.isa2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index b1b946f63..647ceafe3 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -3182,9 +3182,9 @@ let {{
sveBinInst('bic', 'BicPred', 'SimdAluOp', unsignedTypes, bicCode,
PredType.MERGE, True)
# BIC (vectors, unpredicated)
- bicCode = 'destElem = srcElem1 & ~srcElem2;'
sveBinInst('bic', 'BicUnpred', 'SimdAluOp', unsignedTypes, bicCode)
# BIC, BICS (predicates)
+ bicCode = 'destElem = srcElem1 && !srcElem2;'
svePredLogicalInst('bic', 'PredBic', 'SimdPredAluOp', ('uint8_t',),
bicCode)
svePredLogicalInst('bics', 'PredBics', 'SimdPredAluOp', ('uint8_t',),