8 files changed, 17 insertions, 18 deletions
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index c5a8122dd..4a6b3e7cd 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -40,11 +40,11 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from m5.objects.MemObject import MemObject
 from m5.objects.BaseTLB import BaseTLB
+from m5.objects.ClockedObject import ClockedObject
 
 # Basic stage 1 translation objects
-class ArmTableWalker(MemObject):
+class ArmTableWalker(ClockedObject):
     type = 'ArmTableWalker'
     cxx_class = 'ArmISA::TableWalker'
     cxx_header = "arch/arm/table_walker.hh"
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index d310e9ee6..6f06b7112 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -57,7 +57,7 @@
 using namespace ArmISA;
 
 TableWalker::TableWalker(const Params *p)
-    : MemObject(p),
+    : ClockedObject(p),
       stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId),
       isStage2(p->is_stage2), tlb(NULL),
       currState(NULL), pending(false),
@@ -124,7 +124,7 @@ TableWalker::getPort(const std::string &if_name, PortID idx)
             fatal("Cannot access table walker port through stage-two walker\n");
         }
     }
-    return MemObject::getPort(if_name, idx);
+    return ClockedObject::getPort(if_name, idx);
 }
 
 TableWalker::WalkerState::WalkerState() :
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 8176fc7f5..752b57a64 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -48,6 +48,7 @@
 #include "arch/arm/tlb.hh"
 #include "mem/request.hh"
 #include "params/ArmTableWalker.hh"
+#include "sim/clocked_object.hh"
 #include "sim/eventq.hh"
 
 class ThreadContext;
@@ -59,7 +60,7 @@ class Translation;
 class TLB;
 class Stage2MMU;
 
-class TableWalker : public MemObject
+class TableWalker : public ClockedObject
 {
   public:
     class WalkerState;
diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py
index 688117a66..64531b9c5 100644
--- a/src/arch/generic/BaseTLB.py
+++ b/src/arch/generic/BaseTLB.py
@@ -29,9 +29,9 @@
 #          Ivan Pizarro
 
 from m5.params import *
-from m5.objects.MemObject import MemObject
+from m5.SimObject import SimObject
 
-class BaseTLB(MemObject):
+class BaseTLB(SimObject):
     type = 'BaseTLB'
     abstract = True
     cxx_header = "arch/generic/tlb.hh"
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index ba07b1057..cd33ef4c9 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -44,18 +44,16 @@
 #define __ARCH_GENERIC_TLB_HH__
 
 #include "base/logging.hh"
-#include "mem/mem_object.hh"
 #include "mem/request.hh"
+#include "sim/sim_object.hh"
 
 class ThreadContext;
 class BaseMasterPort;
 
-class BaseTLB : public MemObject
+class BaseTLB : public SimObject
 {
   protected:
-    BaseTLB(const Params *p)
-        : MemObject(p)
-    {}
+    BaseTLB(const Params *p) : SimObject(p) {}
 
   public:
 
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index 1b2f63d1d..2e61d027f 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -39,9 +39,9 @@ from m5.params import *
 from m5.proxy import *
 
 from m5.objects.BaseTLB import BaseTLB
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
 
-class X86PagetableWalker(MemObject):
+class X86PagetableWalker(ClockedObject):
     type = 'X86PagetableWalker'
     cxx_class = 'X86ISA::Walker'
     cxx_header = 'arch/x86/pagetable_walker.hh'
diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc
index 0741dc2ed..932eb8eef 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -173,7 +173,7 @@ Walker::getPort(const std::string &if_name, PortID idx)
     if (if_name == "port")
         return port;
     else
-        return MemObject::getPort(if_name, idx);
+        return ClockedObject::getPort(if_name, idx);
 }
 
 void
diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh
index c1f4ed2c4..88b8147cf 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -45,9 +45,9 @@
 #include "arch/x86/pagetable.hh"
 #include "arch/x86/tlb.hh"
 #include "base/types.hh"
-#include "mem/mem_object.hh"
 #include "mem/packet.hh"
 #include "params/X86PagetableWalker.hh"
+#include "sim/clocked_object.hh"
 #include "sim/faults.hh"
 #include "sim/system.hh"
 
@@ -55,7 +55,7 @@ class ThreadContext;
 
 namespace X86ISA
 {
-    class Walker : public MemObject
+    class Walker : public ClockedObject
     {
       protected:
         // Port for accessing memory
@@ -201,7 +201,7 @@ namespace X86ISA
         }
 
         Walker(const Params *params) :
-            MemObject(params), port(name() + ".port", this),
+            ClockedObject(params), port(name() + ".port", this),
             funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system),
             masterId(sys->getMasterId(this)),
             numSquashable(params->num_squash_per_cycle),