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-rw-r--r--src/arch/alpha/registers.hh1
-rw-r--r--src/arch/mips/registers.hh1
-rw-r--r--src/arch/null/registers.hh1
-rw-r--r--src/arch/power/registers.hh1
-rw-r--r--src/arch/riscv/registers.hh1
-rw-r--r--src/arch/x86/registers.hh1
6 files changed, 0 insertions, 6 deletions
diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 2bff11b5c..6c71320b6 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -48,7 +48,6 @@ const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
typedef RegVal IntReg;
// floating point register file entry type
-typedef FloatRegVal FloatReg;
typedef RegVal FloatRegBits;
// control register file contents
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index d2095d84d..6f7097b08 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -282,7 +282,6 @@ typedef RegVal IntReg;
// floating point register file entry type
typedef RegVal FloatRegBits;
-typedef FloatRegVal FloatReg;
// cop-0/cop-1 system control register
typedef RegVal MiscReg;
diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index 527193cc4..fb815af4a 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -48,7 +48,6 @@ namespace NullISA {
typedef RegVal IntReg;
typedef RegVal FloatRegBits;
-typedef FloatRegVal FloatReg;
typedef uint8_t CCReg;
typedef RegVal MiscReg;
const RegIndex ZeroReg = 0;
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 39f7d34f8..989b4c52a 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -49,7 +49,6 @@ typedef RegVal IntReg;
// Floating point register file entry type
typedef RegVal FloatRegBits;
-typedef FloatRegVal FloatReg;
typedef RegVal MiscReg;
// dummy typedef since we don't have CC regs
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 75f74ef2d..2de154e22 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -65,7 +65,6 @@ const int MaxMiscDestRegs = 1;
typedef RegVal IntReg;
typedef RegVal FloatRegBits;
-typedef FloatRegVal FloatReg;
typedef uint8_t CCReg; // Not applicable to Riscv
typedef RegVal MiscReg;
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index a2a74cc4a..509f7a111 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -105,7 +105,6 @@ constexpr unsigned NumVecRegs = 1;
//These floating point types are correct for mmx, but not
//technically for x87 (80 bits) or at all for xmm (128 bits)
-typedef FloatRegVal FloatReg;
typedef RegVal FloatRegBits;
} // namespace X86ISA