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-rw-r--r--src/base/annotate.cc2
-rw-r--r--src/base/bigint.cc47
-rw-r--r--src/base/bigint.hh19
-rw-r--r--src/base/loader/elf_object.cc6
-rw-r--r--src/base/misc.cc2
-rw-r--r--src/base/pollevent.cc2
-rw-r--r--src/base/pollevent.hh2
-rw-r--r--src/base/trace.hh2
-rw-r--r--src/base/traceflags.py1
9 files changed, 78 insertions, 5 deletions
diff --git a/src/base/annotate.cc b/src/base/annotate.cc
index ba2fb1788..de7eeed51 100644
--- a/src/base/annotate.cc
+++ b/src/base/annotate.cc
@@ -32,7 +32,7 @@
#include "base/callback.hh"
#include "base/output.hh"
#include "base/trace.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"
diff --git a/src/base/bigint.cc b/src/base/bigint.cc
new file mode 100644
index 000000000..ce9942c9c
--- /dev/null
+++ b/src/base/bigint.cc
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "base/bigint.hh"
+
+#include <iostream>
+
+using namespace std;
+
+ostream & operator << (ostream & os, const Twin64_t & t)
+{
+ os << t.a << ", " << t.b;
+ return os;
+}
+
+ostream & operator << (ostream & os, const Twin32_t & t)
+{
+ os << t.a << ", " << t.b;
+ return os;
+}
diff --git a/src/base/bigint.hh b/src/base/bigint.hh
index d533e662a..ed48c67fe 100644
--- a/src/base/bigint.hh
+++ b/src/base/bigint.hh
@@ -28,12 +28,21 @@
* Authors: Ali Saidi
*/
+#include <iostream>
+
#ifndef __BASE_BIGINT_HH__
#define __BASE_BIGINT_HH__
// Create a couple of large int types for atomic reads
struct m5_twin64_t {
uint64_t a;
uint64_t b;
+ m5_twin64_t()
+ {}
+ m5_twin64_t(const uint64_t x)
+ {
+ a = x;
+ b = x;
+ }
inline m5_twin64_t& operator=(const uint64_t x)
{
a = x;
@@ -45,6 +54,13 @@ struct m5_twin64_t {
struct m5_twin32_t {
uint32_t a;
uint32_t b;
+ m5_twin32_t()
+ {}
+ m5_twin32_t(const uint32_t x)
+ {
+ a = x;
+ b = x;
+ }
inline m5_twin32_t& operator=(const uint32_t x)
{
a = x;
@@ -59,6 +75,9 @@ struct m5_twin32_t {
typedef m5_twin64_t Twin64_t;
typedef m5_twin32_t Twin32_t;
+// Output operator overloads
+std::ostream & operator << (std::ostream & os, const Twin64_t & t);
+std::ostream & operator << (std::ostream & os, const Twin32_t & t);
#endif // __BASE_BIGINT_HH__
diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc
index b56dc5aa6..8f157da28 100644
--- a/src/base/loader/elf_object.cc
+++ b/src/base/loader/elf_object.cc
@@ -89,6 +89,12 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data)
} else if (ehdr.e_machine == EM_MIPS
&& ehdr.e_ident[EI_CLASS] == ELFCLASS32) {
arch = ObjectFile::Mips;
+ } else if (ehdr.e_machine == EM_X86_64 &&
+ ehdr.e_ident[EI_CLASS] == ELFCLASS64) {
+ //In the future, we might want to differentiate between 32 bit
+ //and 64 bit x86 processes in case there are differences in their
+ //initial stack frame.
+ arch = ObjectFile::X86;
} else if (ehdr.e_ident[EI_CLASS] == ELFCLASS64) {
arch = ObjectFile::Alpha;
} else {
diff --git a/src/base/misc.cc b/src/base/misc.cc
index 29b6d2d88..afb48ca80 100644
--- a/src/base/misc.cc
+++ b/src/base/misc.cc
@@ -38,7 +38,7 @@
#include "base/trace.hh"
#include "base/varargs.hh"
#include "sim/host.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
using namespace std;
diff --git a/src/base/pollevent.cc b/src/base/pollevent.cc
index 32724b74d..331b5eac6 100644
--- a/src/base/pollevent.cc
+++ b/src/base/pollevent.cc
@@ -42,7 +42,7 @@
#include "sim/host.hh"
#include "base/misc.hh"
#include "base/pollevent.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
#include "sim/serialize.hh"
using namespace std;
diff --git a/src/base/pollevent.hh b/src/base/pollevent.hh
index 5b84650cb..ecaeb94ce 100644
--- a/src/base/pollevent.hh
+++ b/src/base/pollevent.hh
@@ -33,7 +33,7 @@
#include <vector>
#include <poll.h>
-#include "sim/root.hh"
+#include "sim/core.hh"
class Checkpoint;
class PollQueue;
diff --git a/src/base/trace.hh b/src/base/trace.hh
index 8e380d8e1..c1b506187 100644
--- a/src/base/trace.hh
+++ b/src/base/trace.hh
@@ -39,7 +39,7 @@
#include "base/match.hh"
#include "base/traceflags.hh"
#include "sim/host.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
namespace Trace {
diff --git a/src/base/traceflags.py b/src/base/traceflags.py
index ba6aa6af8..cb17d98d3 100644
--- a/src/base/traceflags.py
+++ b/src/base/traceflags.py
@@ -168,6 +168,7 @@ baseFlags = [
'VtoPhys',
'WriteBarrier',
'Writeback',
+ 'X86',
]
#