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-rw-r--r--src/cpu/BaseCPU.py7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 50a8501e2..19464acbc 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -138,9 +138,12 @@ class BaseCPU(MemObject):
tracer = Param.InstTracer(default_tracer, "Instruction tracer")
- _cached_ports = []
+ icache_port = Port("Instruction Port")
+ dcache_port = Port("Data Port")
+ _cached_ports = ['icache_port', 'dcache_port']
+
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
- _cached_ports = ["itb.walker.port", "dtb.walker.port"]
+ _cached_ports += ["itb.walker.port", "dtb.walker.port"]
_uncached_ports = []
if buildEnv['TARGET_ISA'] == 'x86':