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Diffstat (limited to 'src/cpu/BaseCPU.py')
| -rw-r--r-- | src/cpu/BaseCPU.py | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 9ed2cb789..8c658b196 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -145,9 +145,6 @@ class BaseCPU(MemObject): defer_registration = Param.Bool(False, "defer registration with system (for sampling)") - clock = Param.Clock('1t', "clock speed") - phase = Param.Latency('0ns', "clock phase") - tracer = Param.InstTracer(default_tracer, "Instruction tracer") icache_port = MasterPort("Instruction Port") |