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-rw-r--r--src/cpu/BaseCPU.py6
1 files changed, 1 insertions, 5 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 331957749..dfbd459fd 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -76,11 +76,7 @@ elif buildEnv['TARGET_ISA'] == 'power':
class BaseCPU(MemObject):
type = 'BaseCPU'
abstract = True
-
- @classmethod
- def export_method_cxx_predecls(cls, code):
- code('#include "cpu/base.hh"')
-
+ cxx_header = "cpu/base.hh"
@classmethod
def export_methods(cls, code):