diff options
Diffstat (limited to 'src/cpu/BaseCPU.py')
| -rw-r--r-- | src/cpu/BaseCPU.py | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 096aa635e..e02d36724 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -42,6 +42,8 @@ # Andreas Hansson # Glenn Bergmans +from __future__ import print_function + import sys from m5.SimObject import * @@ -200,8 +202,8 @@ class BaseCPU(MemObject): [], "Interrupt Controller") isa = VectorParam.RiscvISA([], "ISA instance") else: - print "Don't know what TLB to use for ISA %s" % \ - buildEnv['TARGET_ISA'] + print("Don't know what TLB to use for ISA %s" % + buildEnv['TARGET_ISA']) sys.exit(1) max_insts_all_threads = Param.Counter(0, @@ -260,8 +262,8 @@ class BaseCPU(MemObject): self.interrupts = \ [RiscvInterrupts() for i in xrange(self.numThreads)] else: - print "Don't know what Interrupt Controller to use for ISA %s" % \ - buildEnv['TARGET_ISA'] + print("Don't know what Interrupt Controller to use for ISA %s" % + buildEnv['TARGET_ISA']) sys.exit(1) def connectCachedPorts(self, bus): |