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Diffstat (limited to 'src/cpu/BaseCPU.py')
| -rw-r--r-- | src/cpu/BaseCPU.py | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 6e5f6ff1a..331957749 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -236,7 +236,10 @@ class BaseCPU(MemObject): def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) - self.toL2Bus = CoherentBus() + # Override the default bus clock of 1 GHz and uses the CPU + # clock for the L1-to-L2 bus, and also set a width of 32 bytes + # (256-bits), which is four times that of the default bus. + self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32) self.connectCachedPorts(self.toL2Bus) self.l2cache = l2c self.toL2Bus.master = self.l2cache.cpu_side |