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-rw-r--r--src/cpu/BaseCPU.py3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 900a23991..759bc0881 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -51,6 +51,7 @@ from Bus import CoherentBus
from InstTracer import InstTracer
from ExeTracer import ExeTracer
from MemObject import MemObject
+from BranchPredictor import BranchPredictor
default_tracer = ExeTracer()
@@ -184,6 +185,8 @@ class BaseCPU(MemObject):
dcache_port = MasterPort("Data Port")
_cached_ports = ['icache_port', 'dcache_port']
+ branchPred = Param.BranchPredictor(NULL, "Branch Predictor")
+
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
_cached_ports += ["itb.walker.port", "dtb.walker.port"]