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-rw-r--r--src/cpu/BaseCPU.py6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 6c2aace51..8be84392d 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -31,8 +31,12 @@ from m5.params import *
from m5.proxy import *
from m5 import build_env
from Bus import Bus
+from InstTracer import InstTracer
+from ExeTracer import ExeTracer
import sys
+default_tracer = ExeTracer()
+
if build_env['FULL_SYSTEM']:
if build_env['TARGET_ISA'] == 'alpha':
from AlphaTLB import AlphaDTB, AlphaITB
@@ -83,6 +87,8 @@ class BaseCPU(SimObject):
clock = Param.Clock('1t', "clock speed")
phase = Param.Latency('0ns', "clock phase")
+ tracer = Param.InstTracer(default_tracer, "Instruction tracer")
+
_mem_ports = []
def connectMemPorts(self, bus):