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-rw-r--r--src/cpu/BaseCPU.py3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 1ff4c85b4..b5c203742 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -81,8 +81,7 @@ class BaseCPU(MemObject):
profile = Param.Latency('0ns', "trace the kernel stack")
do_quiesce = Param.Bool(True, "enable quiesce instructions")
- if not buildEnv['FULL_SYSTEM']:
- workload = VectorParam.Process("processes to run")
+ workload = VectorParam.Process([], "processes to run")
if buildEnv['TARGET_ISA'] == 'sparc':
dtb = Param.SparcTLB(SparcTLB(), "Data TLB")