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-rw-r--r--src/cpu/BaseCPU.py89
1 files changed, 37 insertions, 52 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 77ba35b19..fda0a3bc8 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -43,28 +43,22 @@ default_tracer = ExeTracer()
if buildEnv['TARGET_ISA'] == 'alpha':
from AlphaTLB import AlphaDTB, AlphaITB
- if buildEnv['FULL_SYSTEM']:
- from AlphaInterrupts import AlphaInterrupts
+ from AlphaInterrupts import AlphaInterrupts
elif buildEnv['TARGET_ISA'] == 'sparc':
from SparcTLB import SparcTLB
- if buildEnv['FULL_SYSTEM']:
- from SparcInterrupts import SparcInterrupts
+ from SparcInterrupts import SparcInterrupts
elif buildEnv['TARGET_ISA'] == 'x86':
from X86TLB import X86TLB
- if buildEnv['FULL_SYSTEM']:
- from X86LocalApic import X86LocalApic
+ from X86LocalApic import X86LocalApic
elif buildEnv['TARGET_ISA'] == 'mips':
from MipsTLB import MipsTLB
- if buildEnv['FULL_SYSTEM']:
- from MipsInterrupts import MipsInterrupts
+ from MipsInterrupts import MipsInterrupts
elif buildEnv['TARGET_ISA'] == 'arm':
from ArmTLB import ArmTLB
- if buildEnv['FULL_SYSTEM']:
- from ArmInterrupts import ArmInterrupts
+ from ArmInterrupts import ArmInterrupts
elif buildEnv['TARGET_ISA'] == 'power':
from PowerTLB import PowerTLB
- if buildEnv['FULL_SYSTEM']:
- from PowerInterrupts import PowerInterrupts
+ from PowerInterrupts import PowerInterrupts
class BaseCPU(MemObject):
type = 'BaseCPU'
@@ -84,50 +78,42 @@ class BaseCPU(MemObject):
do_statistics_insts = Param.Bool(True,
"enable statistics pseudo instructions")
- if buildEnv['FULL_SYSTEM']:
- profile = Param.Latency('0ns', "trace the kernel stack")
- do_quiesce = Param.Bool(True, "enable quiesce instructions")
- else:
- workload = VectorParam.Process("processes to run")
+ profile = Param.Latency('0ns', "trace the kernel stack")
+ do_quiesce = Param.Bool(True, "enable quiesce instructions")
+
+ workload = VectorParam.Process([], "processes to run")
if buildEnv['TARGET_ISA'] == 'sparc':
dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
- if buildEnv['FULL_SYSTEM']:
- interrupts = Param.SparcInterrupts(
+ interrupts = Param.SparcInterrupts(
SparcInterrupts(), "Interrupt Controller")
elif buildEnv['TARGET_ISA'] == 'alpha':
dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
- if buildEnv['FULL_SYSTEM']:
- interrupts = Param.AlphaInterrupts(
+ interrupts = Param.AlphaInterrupts(
AlphaInterrupts(), "Interrupt Controller")
elif buildEnv['TARGET_ISA'] == 'x86':
dtb = Param.X86TLB(X86TLB(), "Data TLB")
itb = Param.X86TLB(X86TLB(), "Instruction TLB")
- if buildEnv['FULL_SYSTEM']:
- _localApic = X86LocalApic(pio_addr=0x2000000000000000)
- interrupts = \
- Param.X86LocalApic(_localApic, "Interrupt Controller")
+ _localApic = X86LocalApic(pio_addr=0x2000000000000000)
+ interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller")
elif buildEnv['TARGET_ISA'] == 'mips':
dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
- if buildEnv['FULL_SYSTEM']:
- interrupts = Param.MipsInterrupts(
- MipsInterrupts(), "Interrupt Controller")
+ interrupts = Param.MipsInterrupts(
+ MipsInterrupts(), "Interrupt Controller")
elif buildEnv['TARGET_ISA'] == 'arm':
dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
- if buildEnv['FULL_SYSTEM']:
- interrupts = Param.ArmInterrupts(
- ArmInterrupts(), "Interrupt Controller")
+ interrupts = Param.ArmInterrupts(
+ ArmInterrupts(), "Interrupt Controller")
elif buildEnv['TARGET_ISA'] == 'power':
UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
- if buildEnv['FULL_SYSTEM']:
- interrupts = Param.PowerInterrupts(
- PowerInterrupts(), "Interrupt Controller")
+ interrupts = Param.PowerInterrupts(
+ PowerInterrupts(), "Interrupt Controller")
else:
print "Don't know what TLB to use for ISA %s" % \
buildEnv['TARGET_ISA']
@@ -156,11 +142,11 @@ class BaseCPU(MemObject):
dcache_port = Port("Data Port")
_cached_ports = ['icache_port', 'dcache_port']
- if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']:
+ if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
_cached_ports += ["itb.walker.port", "dtb.walker.port"]
_uncached_ports = []
- if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
+ if buildEnv['TARGET_ISA'] == 'x86':
_uncached_ports = ["interrupts.pio", "interrupts.int_port"]
def connectCachedPorts(self, bus):
@@ -183,22 +169,21 @@ class BaseCPU(MemObject):
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
- if buildEnv['FULL_SYSTEM']:
- if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
- if iwc and dwc:
- self.itb_walker_cache = iwc
- self.dtb_walker_cache = dwc
- self.itb.walker.port = iwc.cpu_side
- self.dtb.walker.port = dwc.cpu_side
- self._cached_ports += ["itb_walker_cache.mem_side", \
- "dtb_walker_cache.mem_side"]
- else:
- self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
- # Checker doesn't need its own tlb caches because it does
- # functional accesses only
- if buildEnv['USE_CHECKER']:
- self._cached_ports += ["checker.itb.walker.port", \
- "checker.dtb.walker.port"]
+ if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+ if iwc and dwc:
+ self.itb_walker_cache = iwc
+ self.dtb_walker_cache = dwc
+ self.itb.walker.port = iwc.cpu_side
+ self.dtb.walker.port = dwc.cpu_side
+ self._cached_ports += ["itb_walker_cache.mem_side", \
+ "dtb_walker_cache.mem_side"]
+ else:
+ self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
+ # Checker doesn't need its own tlb caches because it does
+ # functional accesses only
+ if buildEnv['USE_CHECKER']:
+ self._cached_ports += ["checker.itb.walker.port", \
+ "checker.dtb.walker.port"]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)