diff options
Diffstat (limited to 'src/cpu/BaseCPU.py')
| -rw-r--r-- | src/cpu/BaseCPU.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 6640f3cea..430356004 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -140,7 +140,8 @@ class BaseCPU(MemObject): tracer = Param.InstTracer(default_tracer, "Instruction tracer") _cached_ports = [] - if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']: + if buildEnv['TARGET_ISA'] == 'x86' or \ + (buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']): _cached_ports = ["itb.walker.port", "dtb.walker.port"] _uncached_ports = [] |