diff options
Diffstat (limited to 'src/cpu/FuncUnit.py')
| -rw-r--r-- | src/cpu/FuncUnit.py | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py index a408de3ab..21e37be87 100644 --- a/src/cpu/FuncUnit.py +++ b/src/cpu/FuncUnit.py @@ -1,4 +1,4 @@ -# Copyright (c) 2010,2018 ARM Limited +# Copyright (c) 2010, 2017-2018 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -47,13 +47,16 @@ class OpClass(Enum): 'FloatMisc', 'FloatSqrt', 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc', - 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', - 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', - 'SimdFloatMultAcc', 'SimdFloatSqrt', + 'SimdDiv', 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', + 'SimdFloatCmp', 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', + 'SimdFloatMult', 'SimdFloatMultAcc', 'SimdFloatSqrt', + 'SimdReduceAdd', 'SimdReduceAlu', 'SimdReduceCmp', + 'SimdFloatReduceAdd', 'SimdFloatReduceCmp', 'SimdAes', 'SimdAesMix', 'SimdSha1Hash', 'SimdSha1Hash2', 'SimdSha256Hash', 'SimdSha256Hash2', 'SimdShaSigma2', - 'SimdShaSigma3', 'MemRead', 'MemWrite', - 'FloatMemRead', 'FloatMemWrite', + 'SimdShaSigma3', + 'SimdPredAlu', + 'MemRead', 'MemWrite', 'FloatMemRead', 'FloatMemWrite', 'IprAccess', 'InstPrefetch'] class OpDesc(SimObject): |