diff options
Diffstat (limited to 'src/cpu/base.hh')
-rw-r--r-- | src/cpu/base.hh | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 79700c117..43122f238 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -24,6 +24,9 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + * Nathan Binkert */ #ifndef __CPU_BASE_HH__ @@ -38,10 +41,10 @@ #include "sim/sim_object.hh" #include "arch/isa_traits.hh" -class System; -namespace Kernel { class Statistics; } class BranchPred; -class ExecContext; +class CheckerCPU; +class ThreadContext; +class System; class BaseCPU : public SimObject { @@ -89,7 +92,7 @@ class BaseCPU : public SimObject #endif protected: - std::vector<ExecContext *> execContexts; + std::vector<ThreadContext *> threadContexts; public: @@ -125,6 +128,7 @@ class BaseCPU : public SimObject int cpu_id; Tick profile; #endif + BaseCPU *checker; Params(); }; @@ -140,7 +144,7 @@ class BaseCPU : public SimObject virtual void activateWhenReady(int tid) {}; - void registerExecContexts(); + void registerThreadContexts(); /// Prepare for another CPU to take over execution. When it is /// is ready (drained pipe) it signals the sampler. @@ -232,10 +236,6 @@ class BaseCPU : public SimObject public: // Number of CPU cycles simulated Stats::Scalar<> numCycles; - -#if FULL_SYSTEM - Kernel::Statistics *kernelStats; -#endif }; #endif // __CPU_BASE_HH__ |