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Diffstat (limited to 'src/cpu/base_dyn_inst.cc')
-rw-r--r--src/cpu/base_dyn_inst.cc168
1 files changed, 126 insertions, 42 deletions
diff --git a/src/cpu/base_dyn_inst.cc b/src/cpu/base_dyn_inst.cc
index bf7c35cad..7ab760ae3 100644
--- a/src/cpu/base_dyn_inst.cc
+++ b/src/cpu/base_dyn_inst.cc
@@ -26,10 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BASE_DYN_INST_CC__
-#define __CPU_BASE_DYN_INST_CC__
-
#include <iostream>
+#include <set>
#include <string>
#include <sstream>
@@ -43,6 +41,8 @@
#include "cpu/base_dyn_inst.hh"
#include "cpu/o3/alpha_impl.hh"
#include "cpu/o3/alpha_cpu.hh"
+#include "cpu/ozone/simple_impl.hh"
+#include "cpu/ozone/ozone_impl.hh"
using namespace std;
using namespace TheISA;
@@ -54,21 +54,23 @@ using namespace TheISA;
unsigned int MyHashFunc(const BaseDynInst *addr)
{
- unsigned a = (unsigned)addr;
- unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
+ unsigned a = (unsigned)addr;
+ unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
- return hash;
+ return hash;
}
-typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc> my_hash_t;
+typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
+my_hash_t;
+
my_hash_t thishash;
#endif
template <class Impl>
-BaseDynInst<Impl>::BaseDynInst(MachInst machInst, Addr inst_PC,
+BaseDynInst<Impl>::BaseDynInst(ExtMachInst machInst, Addr inst_PC,
Addr pred_PC, InstSeqNum seq_num,
FullCPU *cpu)
- : staticInst(machInst), traceData(NULL), cpu(cpu), cpuXC(cpu->cpuXCBase())
+ : staticInst(machInst), traceData(NULL), cpu(cpu)/*, xc(cpu->xcBase())*/
{
seqNum = seq_num;
@@ -83,6 +85,7 @@ template <class Impl>
BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
: staticInst(_staticInst), traceData(NULL)
{
+ seqNum = 0;
initVars();
}
@@ -90,23 +93,40 @@ template <class Impl>
void
BaseDynInst<Impl>::initVars()
{
+ req = NULL;
effAddr = MemReq::inval_addr;
physEffAddr = MemReq::inval_addr;
+ storeSize = 0;
readyRegs = 0;
completed = false;
+ resultReady = false;
canIssue = false;
issued = false;
executed = false;
canCommit = false;
+ committed = false;
squashed = false;
squashedInIQ = false;
+ squashedInLSQ = false;
+ squashedInROB = false;
eaCalcDone = false;
+ memOpDone = false;
+ lqIdx = -1;
+ sqIdx = -1;
+ reachedCommit = false;
blockingInst = false;
recoverInst = false;
+ iqEntry = false;
+ robEntry = false;
+
+ serializeBefore = false;
+ serializeAfter = false;
+ serializeHandled = false;
+
// Eventually make this a parameter.
threadNumber = 0;
@@ -114,22 +134,63 @@ BaseDynInst<Impl>::initVars()
asid = 0;
// Initialize the fault to be unimplemented opcode.
- fault = new UnimplementedOpcodeFault;
+// fault = new UnimplementedOpcodeFault;
+ fault = NoFault;
++instcount;
- DPRINTF(FullCPU, "DynInst: Instruction created. Instcount=%i\n",
- instcount);
+ if (instcount > 1500) {
+ cpu->dumpInsts();
+#ifdef DEBUG
+ dumpSNList();
+#endif
+ assert(instcount <= 1500);
+ }
+
+ DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n",
+ seqNum, instcount);
+
+#ifdef DEBUG
+ cpu->snList.insert(seqNum);
+#endif
}
template <class Impl>
BaseDynInst<Impl>::~BaseDynInst()
{
+ if (req) {
+ req = NULL;
+ }
+
+ if (traceData) {
+ delete traceData;
+ }
+
--instcount;
- DPRINTF(FullCPU, "DynInst: Instruction destroyed. Instcount=%i\n",
- instcount);
+
+ DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n",
+ seqNum, instcount);
+#ifdef DEBUG
+ cpu->snList.erase(seqNum);
+#endif
}
+#ifdef DEBUG
+template <class Impl>
+void
+BaseDynInst<Impl>::dumpSNList()
+{
+ std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
+
+ int count = 0;
+ while (sn_it != cpu->snList.end()) {
+ cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
+ count++;
+ sn_it++;
+ }
+}
+#endif
+
template <class Impl>
void
BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
@@ -139,14 +200,14 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
// state.
// Generate a MemReq so we can translate the effective address.
- MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), 1, flags);
+ MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
req->asid = asid;
// Prefetches never cause faults.
fault = NoFault;
// note this is a local, not BaseDynInst::fault
- Fault trans_fault = cpuXC->translateDataReadReq(req);
+ Fault trans_fault = cpu->translateDataReadReq(req);
if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
// It's a valid address to cacheable space. Record key MemReq
@@ -162,15 +223,6 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
effAddr = physEffAddr = MemReq::inval_addr;
}
- /**
- * @todo
- * Replace the disjoint functional memory with a unified one and remove
- * this hack.
- */
-#if !FULL_SYSTEM
- req->paddr = req->vaddr;
-#endif
-
if (traceData) {
traceData->setAddr(addr);
}
@@ -184,10 +236,10 @@ BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
// will casue a TLB miss trap if necessary... not sure whether
// that's the best thing to do or not. We don't really need the
// MemReq otherwise, since wh64 has no functional effect.
- MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), size, flags);
+ MemReqPtr req = new MemReq(addr, thread->getXCProxy(), size, flags);
req->asid = asid;
- fault = cpuXC->translateDataWriteReq(req);
+ fault = cpu->translateDataWriteReq(req);
if (fault == NoFault && !(req->flags & UNCACHEABLE)) {
// Record key MemReq parameters so we can generate another one
@@ -212,18 +264,18 @@ template <class Impl>
Fault
BaseDynInst<Impl>::copySrcTranslate(Addr src)
{
- MemReqPtr req = new MemReq(src, cpuXC->getProxy(), 64);
+ MemReqPtr req = new MemReq(src, thread->getXCProxy(), 64);
req->asid = asid;
// translate to physical address
- Fault fault = cpuXC->translateDataReadReq(req);
+ Fault fault = cpu->translateDataReadReq(req);
if (fault == NoFault) {
- cpuXC->copySrcAddr = src;
- cpuXC->copySrcPhysAddr = req->paddr;
+ thread->copySrcAddr = src;
+ thread->copySrcPhysAddr = req->paddr;
} else {
- cpuXC->copySrcAddr = 0;
- cpuXC->copySrcPhysAddr = 0;
+ thread->copySrcAddr = 0;
+ thread->copySrcPhysAddr = 0;
}
return fault;
}
@@ -236,18 +288,18 @@ Fault
BaseDynInst<Impl>::copy(Addr dest)
{
uint8_t data[64];
- FunctionalMemory *mem = cpuXC->mem;
- assert(cpuXC->copySrcPhysAddr || cpuXC->misspeculating());
- MemReqPtr req = new MemReq(dest, cpuXC->getProxy(), 64);
+ FunctionalMemory *mem = thread->mem;
+ assert(thread->copySrcPhysAddr || thread->misspeculating());
+ MemReqPtr req = new MemReq(dest, thread->getXCProxy(), 64);
req->asid = asid;
// translate to physical address
- Fault fault = cpuXC->translateDataWriteReq(req);
+ Fault fault = cpu->translateDataWriteReq(req);
if (fault == NoFault) {
Addr dest_addr = req->paddr;
// Need to read straight from memory since we have more than 8 bytes.
- req->paddr = cpuXC->copySrcPhysAddr;
+ req->paddr = thread->copySrcPhysAddr;
mem->read(req, data);
req->paddr = dest_addr;
mem->write(req, data);
@@ -275,7 +327,6 @@ BaseDynInst<Impl>::dump(std::string &outstring)
outstring = s.str();
}
-
#if 0
template <class Impl>
Fault
@@ -338,6 +389,28 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
#endif
template <class Impl>
+void
+BaseDynInst<Impl>::markSrcRegReady()
+{
+ if (++readyRegs == numSrcRegs()) {
+ canIssue = true;
+ }
+}
+
+template <class Impl>
+void
+BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
+{
+ ++readyRegs;
+
+ _readySrcRegIdx[src_idx] = true;
+
+ if (readyRegs == numSrcRegs()) {
+ canIssue = true;
+ }
+}
+
+template <class Impl>
bool
BaseDynInst<Impl>::eaSrcsReady()
{
@@ -345,8 +418,7 @@ BaseDynInst<Impl>::eaSrcsReady()
// EA calc depends on. (i.e. src reg 0 is the source of the data to be
// stored)
- for (int i = 1; i < numSrcRegs(); ++i)
- {
+ for (int i = 1; i < numSrcRegs(); ++i) {
if (!_readySrcRegIdx[i])
return false;
}
@@ -361,4 +433,16 @@ template <>
int
BaseDynInst<AlphaSimpleImpl>::instcount = 0;
-#endif // __CPU_BASE_DYN_INST_CC__
+// Forward declaration
+template class BaseDynInst<SimpleImpl>;
+
+template <>
+int
+BaseDynInst<SimpleImpl>::instcount = 0;
+
+// Forward declaration
+template class BaseDynInst<OzoneImpl>;
+
+template <>
+int
+BaseDynInst<OzoneImpl>::instcount = 0;
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-23 20:00:52 +0000