1 files changed, 140 insertions, 100 deletions

diff --git a/src/cpu/base_dyn_inst.cc b/src/cpu/base_dyn_inst.cc
index 53b2e354e..30fa10a6b 100644
--- a/src/cpu/base_dyn_inst.cc
+++ b/src/cpu/base_dyn_inst.cc
@@ -28,10 +28,8 @@
  * Authors: Kevin Lim
  */
 
-#ifndef __CPU_BASE_DYN_INST_CC__
-#define __CPU_BASE_DYN_INST_CC__
-
 #include <iostream>
+#include <set>
 #include <string>
 #include <sstream>
 
@@ -40,11 +38,13 @@
 
 #include "arch/faults.hh"
 #include "cpu/exetrace.hh"
-#include "mem/mem_req.hh"
+#include "mem/request.hh"
 
 #include "cpu/base_dyn_inst.hh"
 #include "cpu/o3/alpha_impl.hh"
 #include "cpu/o3/alpha_cpu.hh"
+//#include "cpu/ozone/simple_impl.hh"
+//#include "cpu/ozone/ozone_impl.hh"
 
 using namespace std;
 using namespace TheISA;
@@ -56,21 +56,23 @@ using namespace TheISA;
 
 unsigned int MyHashFunc(const BaseDynInst *addr)
 {
-  unsigned a = (unsigned)addr;
-  unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
+    unsigned a = (unsigned)addr;
+    unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
 
-  return hash;
+    return hash;
 }
 
-typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc> my_hash_t;
+typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
+my_hash_t;
+
 my_hash_t thishash;
 #endif
 
 template <class Impl>
-BaseDynInst<Impl>::BaseDynInst(MachInst machInst, Addr inst_PC,
+BaseDynInst<Impl>::BaseDynInst(ExtMachInst machInst, Addr inst_PC,
                                Addr pred_PC, InstSeqNum seq_num,
                                FullCPU *cpu)
-    : staticInst(machInst), traceData(NULL), cpu(cpu), cpuXC(cpu->cpuXCBase())
+  : staticInst(machInst), traceData(NULL), cpu(cpu)/*, xc(cpu->xcBase())*/
 {
     seqNum = seq_num;
 
@@ -85,6 +87,7 @@ template <class Impl>
 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
     : staticInst(_staticInst), traceData(NULL)
 {
+    seqNum = 0;
     initVars();
 }
 
@@ -92,46 +95,111 @@ template <class Impl>
 void
 BaseDynInst<Impl>::initVars()
 {
-    effAddr = MemReq::inval_addr;
-    physEffAddr = MemReq::inval_addr;
+    req = NULL;
+    memData = NULL;
+    effAddr = 0;
+    physEffAddr = 0;
+    storeSize = 0;
 
     readyRegs = 0;
 
+    // May want to turn this into a bit vector or something.
     completed = false;
+    resultReady = false;
     canIssue = false;
     issued = false;
     executed = false;
     canCommit = false;
+    committed = false;
     squashed = false;
     squashedInIQ = false;
+    squashedInLSQ = false;
+    squashedInROB = false;
     eaCalcDone = false;
+    memOpDone = false;
+    lqIdx = -1;
+    sqIdx = -1;
+    reachedCommit = false;
 
     blockingInst = false;
     recoverInst = false;
 
+    iqEntry = false;
+    robEntry = false;
+
+    serializeBefore = false;
+    serializeAfter = false;
+    serializeHandled = false;
+
     // Eventually make this a parameter.
     threadNumber = 0;
 
     // Also make this a parameter, or perhaps get it from xc or cpu.
     asid = 0;
 
-    // Initialize the fault to be unimplemented opcode.
-    fault = new UnimplementedOpcodeFault;
+    // Initialize the fault to be NoFault.
+    fault = NoFault;
 
     ++instcount;
 
-    DPRINTF(FullCPU, "DynInst: Instruction created.  Instcount=%i\n",
-            instcount);
+    if (instcount > 1500) {
+        cpu->dumpInsts();
+#ifdef DEBUG
+        dumpSNList();
+#endif
+        assert(instcount <= 1500);
+    }
+
+    DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n",
+            seqNum, instcount);
+
+#ifdef DEBUG
+    cpu->snList.insert(seqNum);
+#endif
 }
 
 template <class Impl>
 BaseDynInst<Impl>::~BaseDynInst()
 {
+    if (req) {
+        delete req;
+    }
+
+    if (memData) {
+        delete [] memData;
+    }
+
+    if (traceData) {
+        delete traceData;
+    }
+
+    fault = NoFault;
+
     --instcount;
-    DPRINTF(FullCPU, "DynInst: Instruction destroyed.  Instcount=%i\n",
-            instcount);
+
+    DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n",
+            seqNum, instcount);
+#ifdef DEBUG
+    cpu->snList.erase(seqNum);
+#endif
 }
 
+#ifdef DEBUG
+template <class Impl>
+void
+BaseDynInst<Impl>::dumpSNList()
+{
+    std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
+
+    int count = 0;
+    while (sn_it != cpu->snList.end()) {
+        cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
+        count++;
+        sn_it++;
+    }
+}
+#endif
+
 template <class Impl>
 void
 BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
@@ -139,16 +207,16 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
     // This is the "functional" implementation of prefetch.  Not much
     // happens here since prefetches don't affect the architectural
     // state.
-
+/*
     // Generate a MemReq so we can translate the effective address.
-    MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), 1, flags);
+    MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
     req->asid = asid;
 
     // Prefetches never cause faults.
     fault = NoFault;
 
     // note this is a local, not BaseDynInst::fault
-    Fault trans_fault = cpuXC->translateDataReadReq(req);
+    Fault trans_fault = cpu->translateDataReadReq(req);
 
     if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
         // It's a valid address to cacheable space.  Record key MemReq
@@ -164,18 +232,10 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
         effAddr = physEffAddr = MemReq::inval_addr;
     }
 
-    /**
-     * @todo
-     * Replace the disjoint functional memory with a unified one and remove
-     * this hack.
-     */
-#if !FULL_SYSTEM
-    req->paddr = req->vaddr;
-#endif
-
     if (traceData) {
         traceData->setAddr(addr);
     }
+*/
 }
 
 template <class Impl>
@@ -186,10 +246,11 @@ BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
     // will casue a TLB miss trap if necessary... not sure whether
     // that's the best thing to do or not.  We don't really need the
     // MemReq otherwise, since wh64 has no functional effect.
-    MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), size, flags);
+/*
+    MemReqPtr req = new MemReq(addr, thread->getXCProxy(), size, flags);
     req->asid = asid;
 
-    fault = cpuXC->translateDataWriteReq(req);
+    fault = cpu->translateDataWriteReq(req);
 
     if (fault == NoFault && !(req->flags & UNCACHEABLE)) {
         // Record key MemReq parameters so we can generate another one
@@ -205,6 +266,7 @@ BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
 
     storeSize = size;
     storeData = 0;
+*/
 }
 
 /**
@@ -214,20 +276,23 @@ template <class Impl>
 Fault
 BaseDynInst<Impl>::copySrcTranslate(Addr src)
 {
-    MemReqPtr req = new MemReq(src, cpuXC->getProxy(), 64);
+/*
+    MemReqPtr req = new MemReq(src, thread->getXCProxy(), 64);
     req->asid = asid;
 
     // translate to physical address
-    Fault fault = cpuXC->translateDataReadReq(req);
+    Fault fault = cpu->translateDataReadReq(req);
 
     if (fault == NoFault) {
-        cpuXC->copySrcAddr = src;
-        cpuXC->copySrcPhysAddr = req->paddr;
+        thread->copySrcAddr = src;
+        thread->copySrcPhysAddr = req->paddr;
     } else {
-        cpuXC->copySrcAddr = 0;
-        cpuXC->copySrcPhysAddr = 0;
+        thread->copySrcAddr = 0;
+        thread->copySrcPhysAddr = 0;
     }
     return fault;
+*/
+    return NoFault;
 }
 
 /**
@@ -237,24 +302,27 @@ template <class Impl>
 Fault
 BaseDynInst<Impl>::copy(Addr dest)
 {
+/*
     uint8_t data[64];
-    FunctionalMemory *mem = cpuXC->mem;
-    assert(cpuXC->copySrcPhysAddr || cpuXC->misspeculating());
-    MemReqPtr req = new MemReq(dest, cpuXC->getProxy(), 64);
+    FunctionalMemory *mem = thread->mem;
+    assert(thread->copySrcPhysAddr);
+    MemReqPtr req = new MemReq(dest, thread->getXCProxy(), 64);
     req->asid = asid;
 
     // translate to physical address
-    Fault fault = cpuXC->translateDataWriteReq(req);
+    Fault fault = cpu->translateDataWriteReq(req);
 
     if (fault == NoFault) {
         Addr dest_addr = req->paddr;
         // Need to read straight from memory since we have more than 8 bytes.
-        req->paddr = cpuXC->copySrcPhysAddr;
+        req->paddr = thread->copySrcPhysAddr;
         mem->read(req, data);
         req->paddr = dest_addr;
         mem->write(req, data);
     }
     return fault;
+*/
+    return NoFault;
 }
 
 template <class Impl>
@@ -277,68 +345,28 @@ BaseDynInst<Impl>::dump(std::string &outstring)
     outstring = s.str();
 }
 
-
-#if 0
 template <class Impl>
-Fault
-BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
+void
+BaseDynInst<Impl>::markSrcRegReady()
 {
-    Fault fault;
-
-    // check alignments, even speculative this test should always pass
-    if ((nbytes & nbytes - 1) != 0 || (addr & nbytes - 1) != 0) {
-        for (int i = 0; i < nbytes; i++)
-            ((char *) p)[i] = 0;
-
-        // I added the following because according to the comment above,
-        // we should never get here.  The comment lies
-#if 0
-        panic("unaligned access. Cycle = %n", curTick);
-#endif
-        return NoFault;
+    if (++readyRegs == numSrcRegs()) {
+        canIssue = true;
     }
+}
 
-    MemReqPtr req = new MemReq(addr, thread, nbytes);
-    switch(cmd) {
-      case Read:
-        fault = spec_mem->read(req, (uint8_t *)p);
-        break;
-
-      case Write:
-        fault = spec_mem->write(req, (uint8_t *)p);
-        if (fault != NoFault)
-            break;
-
-        specMemWrite = true;
-        storeSize = nbytes;
-        switch(nbytes) {
-          case sizeof(uint8_t):
-            *(uint8_t)&storeData = (uint8_t *)p;
-            break;
-          case sizeof(uint16_t):
-            *(uint16_t)&storeData = (uint16_t *)p;
-            break;
-          case sizeof(uint32_t):
-            *(uint32_t)&storeData = (uint32_t *)p;
-            break;
-          case sizeof(uint64_t):
-            *(uint64_t)&storeData = (uint64_t *)p;
-            break;
-        }
-        break;
-
-      default:
-        fault = genMachineCheckFault();
-        break;
-    }
+template <class Impl>
+void
+BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
+{
+    ++readyRegs;
 
-    trace_mem(fault, cmd, addr, p, nbytes);
+    _readySrcRegIdx[src_idx] = true;
 
-    return fault;
+    if (readyRegs == numSrcRegs()) {
+        canIssue = true;
+    }
 }
 
-#endif
-
 template <class Impl>
 bool
 BaseDynInst<Impl>::eaSrcsReady()
@@ -347,8 +375,7 @@ BaseDynInst<Impl>::eaSrcsReady()
     // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
     // stored)
 
-    for (int i = 1; i < numSrcRegs(); ++i)
-    {
+    for (int i = 1; i < numSrcRegs(); ++i) {
         if (!_readySrcRegIdx[i])
             return false;
     }
@@ -362,5 +389,18 @@ template class BaseDynInst<AlphaSimpleImpl>;
 template <>
 int
 BaseDynInst<AlphaSimpleImpl>::instcount = 0;
+/*
+// Forward declaration
+template class BaseDynInst<SimpleImpl>;
 
-#endif // __CPU_BASE_DYN_INST_CC__
+template <>
+int
+BaseDynInst<SimpleImpl>::instcount = 0;
+
+// Forward declaration
+template class BaseDynInst<OzoneImpl>;
+
+template <>
+int
+BaseDynInst<OzoneImpl>::instcount = 0;
+*/