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-rw-r--r--src/cpu/checker/cpu.hh12
-rw-r--r--src/cpu/checker/cpu_impl.hh4
2 files changed, 8 insertions, 8 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 19d3420ec..637481706 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -213,13 +213,13 @@ class CheckerCPU : public BaseCPU
FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
- int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+ int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
return thread->readFloatReg(reg_idx);
}
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
- int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+ int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
return thread->readFloatRegBits(reg_idx);
}
@@ -239,7 +239,7 @@ class CheckerCPU : public BaseCPU
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
- int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+ int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
thread->setFloatReg(reg_idx, val);
setResult<double>(val);
}
@@ -247,7 +247,7 @@ class CheckerCPU : public BaseCPU
void setFloatRegOperandBits(const StaticInst *si, int idx,
FloatRegBits val)
{
- int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+ int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
thread->setFloatRegBits(reg_idx, val);
setResult<uint64_t>(val);
}
@@ -294,14 +294,14 @@ class CheckerCPU : public BaseCPU
MiscReg readMiscRegOperand(const StaticInst *si, int idx)
{
- int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+ int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
return thread->readMiscReg(reg_idx);
}
void setMiscRegOperand(
const StaticInst *si, int idx, const MiscReg &val)
{
- int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+ int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
return thread->setMiscReg(reg_idx, val);
}
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 1967e02f3..185fed88e 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -607,7 +607,7 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
thread->setFloatRegBits(idx, mismatch_val);
break;
case MiscRegClass:
- thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag,
+ thread->setMiscReg(idx - TheISA::Misc_Reg_Base,
mismatch_val);
break;
}
@@ -626,7 +626,7 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
break;
case MiscRegClass:
// Try to get the proper misc register index for ARM here...
- thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag, res);
+ thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res);
break;
// else Register is out of range...
}