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-rw-r--r--src/cpu/checker/cpu.cc55
-rw-r--r--src/cpu/checker/cpu.hh23
-rw-r--r--src/cpu/checker/cpu_impl.hh9
-rw-r--r--src/cpu/checker/thread_context.hh29
4 files changed, 15 insertions, 101 deletions
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index a6af98d66..14777bc12 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -159,7 +159,7 @@ CheckerCPU::read(Addr addr, T &data, unsigned flags)
memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
// translate to physical address
- translateDataReadReq(memReq);
+ dtb->translateAtomic(memReq, tc, false);
PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
@@ -229,7 +229,7 @@ CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
// translate to physical address
- thread->translateDataWriteReq(memReq);
+ dtb->translateAtomic(memReq, tc, true);
// Can compare the write data and result only if it's cacheable,
// not a store conditional, or is a store conditional that
@@ -325,57 +325,6 @@ CheckerCPU::dbg_vtophys(Addr addr)
#endif // FULL_SYSTEM
bool
-CheckerCPU::translateInstReq(Request *req)
-{
-#if FULL_SYSTEM
- return (thread->translateInstReq(req) == NoFault);
-#else
- thread->translateInstReq(req);
- return true;
-#endif
-}
-
-void
-CheckerCPU::translateDataReadReq(Request *req)
-{
- thread->translateDataReadReq(req);
-
- if (req->getVaddr() != unverifiedReq->getVaddr()) {
- warn("%lli: Request virtual addresses do not match! Inst: %#x, "
- "checker: %#x",
- curTick, unverifiedReq->getVaddr(), req->getVaddr());
- handleError();
- }
- req->setPaddr(unverifiedReq->getPaddr());
-
- if (checkFlags(req)) {
- warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
- curTick, unverifiedReq->getFlags(), req->getFlags());
- handleError();
- }
-}
-
-void
-CheckerCPU::translateDataWriteReq(Request *req)
-{
- thread->translateDataWriteReq(req);
-
- if (req->getVaddr() != unverifiedReq->getVaddr()) {
- warn("%lli: Request virtual addresses do not match! Inst: %#x, "
- "checker: %#x",
- curTick, unverifiedReq->getVaddr(), req->getVaddr());
- handleError();
- }
- req->setPaddr(unverifiedReq->getPaddr());
-
- if (checkFlags(req)) {
- warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
- curTick, unverifiedReq->getFlags(), req->getFlags());
- handleError();
- }
-}
-
-bool
CheckerCPU::checkFlags(Request *req)
{
// Remove any dynamic flags that don't have to do with the request itself.
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 35dc59ff4..0d3dddded 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -65,6 +65,7 @@ class Process;
#endif // FULL_SYSTEM
template <class>
class BaseDynInst;
+class CheckerCPUParams;
class ThreadContext;
class MemInterface;
class Checkpoint;
@@ -96,20 +97,10 @@ class CheckerCPU : public BaseCPU
public:
virtual void init();
- struct Params : public BaseCPU::Params
- {
-#if FULL_SYSTEM
- TheISA::ITB *itb;
- TheISA::DTB *dtb;
-#else
- Process *process;
-#endif
- bool exitOnError;
- bool updateOnError;
- bool warnOnlyOnLoadError;
- };
-
public:
+ typedef CheckerCPUParams Params;
+ const Params *params() const
+ { return reinterpret_cast<const Params *>(_params); }
CheckerCPU(Params *p);
virtual ~CheckerCPU();
@@ -189,7 +180,7 @@ class CheckerCPU : public BaseCPU
// These functions are only used in CPU models that split
// effective address computation from the actual memory access.
void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
- Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
+ Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
void prefetch(Addr addr, unsigned flags)
{
@@ -340,10 +331,6 @@ class CheckerCPU : public BaseCPU
this->dtb->demapPage(vaddr, asn);
}
- bool translateInstReq(Request *req);
- void translateDataWriteReq(Request *req);
- void translateDataReadReq(Request *req);
-
#if FULL_SYSTEM
Fault hwrei() { return thread->hwrei(); }
void ev5_trap(Fault fault) { fault->invoke(tc); }
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index f3f8a0bb3..26571ed68 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -141,9 +141,9 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
// Try to fetch the instruction
#if FULL_SYSTEM
-#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
+#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
#else
-#define IFETCH_FLAGS(pc) 0
+#define IFETCH_FLAGS(pc) 0
#endif
uint64_t fetch_PC = thread->readPC() & ~3;
@@ -152,9 +152,10 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
memReq = new Request(inst->threadNumber, fetch_PC,
sizeof(uint32_t),
IFETCH_FLAGS(thread->readPC()),
- fetch_PC, thread->readCpuId(), inst->threadNumber);
+ fetch_PC, thread->contextId(),
+ inst->threadNumber);
- bool succeeded = translateInstReq(memReq);
+ bool succeeded = itb->translateAtomic(memReq, thread);
if (!succeeded) {
if (inst->getFault() == NoFault) {
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 15454c3fe..3c87f841f 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -82,7 +82,7 @@ class CheckerThreadContext : public ThreadContext
checkerTC->setCpuId(id);
}
- int readCpuId() { return actualTC->readCpuId(); }
+ int cpuId() { return actualTC->cpuId(); }
TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
@@ -98,10 +98,8 @@ class CheckerThreadContext : public ThreadContext
FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
- VirtualPort *getVirtPort(ThreadContext *tc = NULL)
+ VirtualPort *getVirtPort()
{ return actualTC->getVirtPort(); }
-
- void delVirtPort(VirtualPort *vp) { actualTC->delVirtPort(vp); }
#else
TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
@@ -155,7 +153,7 @@ class CheckerThreadContext : public ThreadContext
void profileSample() { return actualTC->profileSample(); }
#endif
- int getThreadNum() { return actualTC->getThreadNum(); }
+ int threadId() { return actualTC->threadId(); }
// @todo: Do I need this?
MachInst getInst() { return actualTC->getInst(); }
@@ -279,29 +277,8 @@ class CheckerThreadContext : public ThreadContext
bool misspeculating() { return actualTC->misspeculating(); }
#if !FULL_SYSTEM
- IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
-
- // used to shift args for indirect syscall
- void setSyscallArg(int i, IntReg val)
- {
- checkerTC->setSyscallArg(i, val);
- actualTC->setSyscallArg(i, val);
- }
-
- void setSyscallReturn(SyscallReturn return_value)
- {
- checkerTC->setSyscallReturn(return_value);
- actualTC->setSyscallReturn(return_value);
- }
-
Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
#endif
- void changeRegFileContext(TheISA::RegContextParam param,
- TheISA::RegContextVal val)
- {
- actualTC->changeRegFileContext(param, val);
- checkerTC->changeRegFileContext(param, val);
- }
};
#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 06:43:33 +0000