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-rw-r--r--src/cpu/checker/cpu.cc4
-rw-r--r--src/cpu/checker/cpu_impl.hh2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index e530e6014..14777bc12 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -159,7 +159,7 @@ CheckerCPU::read(Addr addr, T &data, unsigned flags)
memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
// translate to physical address
- dtb->translate(memReq, tc, false);
+ dtb->translateAtomic(memReq, tc, false);
PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
@@ -229,7 +229,7 @@ CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
// translate to physical address
- dtb->translate(memReq, tc, true);
+ dtb->translateAtomic(memReq, tc, true);
// Can compare the write data and result only if it's cacheable,
// not a store conditional, or is a store conditional that
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index e1ecc151c..26571ed68 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -155,7 +155,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
fetch_PC, thread->contextId(),
inst->threadNumber);
- bool succeeded = itb->translate(memReq, thread);
+ bool succeeded = itb->translateAtomic(memReq, thread);
if (!succeeded) {
if (inst->getFault() == NoFault) {