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-rw-r--r--src/cpu/checker/cpu.cc49
-rw-r--r--src/cpu/checker/cpu.hh5
-rw-r--r--src/cpu/checker/cpu_impl.hh22
3 files changed, 31 insertions, 45 deletions
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 1533d7405..8329e3191 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -69,7 +69,6 @@ CheckerCPU::CheckerCPU(Params *p)
: BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
tc(NULL), thread(NULL)
{
- memReq = NULL;
curStaticInst = NULL;
curMacroStaticInst = NULL;
@@ -156,27 +155,28 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
// Need to account for multiple accesses like the Atomic and TimingSimple
while (1) {
- memReq = new Request(0, addr, size, flags, masterId,
- thread->pcState().instAddr(), tc->contextId());
+ auto mem_req = std::make_shared<Request>(
+ 0, addr, size, flags, masterId,
+ thread->pcState().instAddr(), tc->contextId());
// translate to physical address
- fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
+ fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Read);
if (!checked_flags && fault == NoFault && unverifiedReq) {
- flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
- memReq->getPaddr(), memReq->getFlags());
- pAddr = memReq->getPaddr();
+ flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
+ mem_req->getPaddr(), mem_req->getFlags());
+ pAddr = mem_req->getPaddr();
checked_flags = true;
}
// Now do the access
if (fault == NoFault &&
- !memReq->getFlags().isSet(Request::NO_ACCESS)) {
- PacketPtr pkt = Packet::createRead(memReq);
+ !mem_req->getFlags().isSet(Request::NO_ACCESS)) {
+ PacketPtr pkt = Packet::createRead(mem_req);
pkt->dataStatic(data);
- if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
+ if (!(mem_req->isUncacheable() || mem_req->isMmappedIpr())) {
// Access memory to see if we have the same data
dcachePort->sendFunctional(pkt);
} else {
@@ -184,24 +184,16 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
memcpy(data, unverifiedMemData, size);
}
- delete memReq;
- memReq = NULL;
delete pkt;
}
if (fault != NoFault) {
- if (memReq->isPrefetch()) {
+ if (mem_req->isPrefetch()) {
fault = NoFault;
}
- delete memReq;
- memReq = NULL;
break;
}
- if (memReq != NULL) {
- delete memReq;
- }
-
//If we don't need to access a second cache line, stop now.
if (secondAddr <= addr)
{
@@ -244,16 +236,17 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size,
// Need to account for a multiple access like Atomic and Timing CPUs
while (1) {
- memReq = new Request(0, addr, size, flags, masterId,
- thread->pcState().instAddr(), tc->contextId());
+ auto mem_req = std::make_shared<Request>(
+ 0, addr, size, flags, masterId,
+ thread->pcState().instAddr(), tc->contextId());
// translate to physical address
- fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
+ fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Write);
if (!checked_flags && fault == NoFault && unverifiedReq) {
- flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
- memReq->getPaddr(), memReq->getFlags());
- pAddr = memReq->getPaddr();
+ flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
+ mem_req->getPaddr(), mem_req->getFlags());
+ pAddr = mem_req->getPaddr();
checked_flags = true;
}
@@ -264,9 +257,7 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size,
* enabled. This is left as future work for the Checker: LSQ snooping
* and memory validation after stores have committed.
*/
- bool was_prefetch = memReq->isPrefetch();
-
- delete memReq;
+ bool was_prefetch = mem_req->isPrefetch();
//If we don't need to access a second cache line, stop now.
if (fault != NoFault || secondAddr <= addr)
@@ -337,7 +328,7 @@ CheckerCPU::dbg_vtophys(Addr addr)
* Checks if the flags set by the Checker and Checkee match.
*/
bool
-CheckerCPU::checkFlags(RequestPtr unverified_req, Addr vAddr,
+CheckerCPU::checkFlags(const RequestPtr &unverified_req, Addr vAddr,
Addr pAddr, int flags)
{
Addr unverifiedVAddr = unverified_req->getVaddr();
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 101a16be6..bee72253e 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -144,9 +144,6 @@ class CheckerCPU : public BaseCPU, public ExecContext
// keep them all in a std::queue
std::queue<InstResult> result;
- // Pointer to the one memory request.
- RequestPtr memReq;
-
StaticInstPtr curStaticInst;
StaticInstPtr curMacroStaticInst;
@@ -531,7 +528,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
dumpAndExit();
}
- bool checkFlags(RequestPtr unverified_req, Addr vAddr,
+ bool checkFlags(const RequestPtr &unverified_req, Addr vAddr,
Addr pAddr, int flags);
void dumpAndExit();
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index d81858c14..57282cd13 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -244,16 +244,17 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
// If not in the middle of a macro instruction
if (!curMacroStaticInst) {
// set up memory request for instruction fetch
- memReq = new Request(unverifiedInst->threadNumber, fetch_PC,
- sizeof(MachInst),
- 0,
- masterId,
- fetch_PC, thread->contextId());
- memReq->setVirt(0, fetch_PC, sizeof(MachInst),
- Request::INST_FETCH, masterId, thread->instAddr());
+ auto mem_req = std::make_shared<Request>(
+ unverifiedInst->threadNumber, fetch_PC,
+ sizeof(MachInst), 0, masterId, fetch_PC,
+ thread->contextId());
+ mem_req->setVirt(0, fetch_PC, sizeof(MachInst),
+ Request::INST_FETCH, masterId,
+ thread->instAddr());
- fault = itb->translateFunctional(memReq, tc, BaseTLB::Execute);
+ fault = itb->translateFunctional(
+ mem_req, tc, BaseTLB::Execute);
if (fault != NoFault) {
if (unverifiedInst->getFault() == NoFault) {
@@ -270,7 +271,6 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
advancePC(NoFault);
// Give up on an ITB fault..
- delete memReq;
unverifiedInst = NULL;
return;
} else {
@@ -278,17 +278,15 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
// the fault and see if our results match the CPU on
// the next tick().
fault = unverifiedInst->getFault();
- delete memReq;
break;
}
} else {
- PacketPtr pkt = new Packet(memReq, MemCmd::ReadReq);
+ PacketPtr pkt = new Packet(mem_req, MemCmd::ReadReq);
pkt->dataStatic(&machInst);
icachePort->sendFunctional(pkt);
machInst = gtoh(machInst);
- delete memReq;
delete pkt;
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 11:39:19 +0000