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-rw-r--r--src/cpu/checker/cpu.hh65
-rw-r--r--src/cpu/checker/cpu_impl.hh24
-rw-r--r--src/cpu/checker/thread_context.hh7
3 files changed, 48 insertions, 48 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 3afbc31fb..304caaa85 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -213,31 +213,31 @@ class CheckerCPU : public BaseCPU, public ExecContext
IntReg readIntRegOperand(const StaticInst *si, int idx) override
{
- RegId reg = si->srcRegIdx(idx);
- assert(reg.regClass == IntRegClass);
- return thread->readIntReg(reg.regIdx);
+ const RegId& reg = si->srcRegIdx(idx);
+ assert(reg.isIntReg());
+ return thread->readIntReg(reg.index());
}
FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
{
- RegId reg = si->srcRegIdx(idx);
- assert(reg.regClass == FloatRegClass);
- return thread->readFloatReg(reg.regIdx);
+ const RegId& reg = si->srcRegIdx(idx);
+ assert(reg.isFloatReg());
+ return thread->readFloatReg(reg.index());
}
FloatRegBits readFloatRegOperandBits(const StaticInst *si,
int idx) override
{
- RegId reg = si->srcRegIdx(idx);
- assert(reg.regClass == FloatRegClass);
- return thread->readFloatRegBits(reg.regIdx);
+ const RegId& reg = si->srcRegIdx(idx);
+ assert(reg.isFloatReg());
+ return thread->readFloatRegBits(reg.index());
}
CCReg readCCRegOperand(const StaticInst *si, int idx) override
{
- RegId reg = si->srcRegIdx(idx);
- assert(reg.regClass == CCRegClass);
- return thread->readCCReg(reg.regIdx);
+ const RegId& reg = si->srcRegIdx(idx);
+ assert(reg.isCCReg());
+ return thread->readCCReg(reg.index());
}
template <class T>
@@ -251,35 +251,35 @@ class CheckerCPU : public BaseCPU, public ExecContext
void setIntRegOperand(const StaticInst *si, int idx,
IntReg val) override
{
- RegId reg = si->destRegIdx(idx);
- assert(reg.regClass == IntRegClass);
- thread->setIntReg(reg.regIdx, val);
+ const RegId& reg = si->destRegIdx(idx);
+ assert(reg.isIntReg());
+ thread->setIntReg(reg.index(), val);
setResult<uint64_t>(val);
}
void setFloatRegOperand(const StaticInst *si, int idx,
FloatReg val) override
{
- RegId reg = si->destRegIdx(idx);
- assert(reg.regClass == FloatRegClass);
- thread->setFloatReg(reg.regIdx, val);
+ const RegId& reg = si->destRegIdx(idx);
+ assert(reg.isFloatReg());
+ thread->setFloatReg(reg.index(), val);
setResult<double>(val);
}
void setFloatRegOperandBits(const StaticInst *si, int idx,
FloatRegBits val) override
{
- RegId reg = si->destRegIdx(idx);
- assert(reg.regClass == FloatRegClass);
- thread->setFloatRegBits(reg.regIdx, val);
+ const RegId& reg = si->destRegIdx(idx);
+ assert(reg.isFloatReg());
+ thread->setFloatRegBits(reg.index(), val);
setResult<uint64_t>(val);
}
void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
{
- RegId reg = si->destRegIdx(idx);
- assert(reg.regClass == CCRegClass);
- thread->setCCReg(reg.regIdx, val);
+ const RegId& reg = si->destRegIdx(idx);
+ assert(reg.isCCReg());
+ thread->setCCReg(reg.index(), val);
setResult<uint64_t>(val);
}
@@ -327,27 +327,28 @@ class CheckerCPU : public BaseCPU, public ExecContext
MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
{
- RegId reg = si->srcRegIdx(idx);
- assert(reg.regClass == MiscRegClass);
- return thread->readMiscReg(reg.regIdx);
+ const RegId& reg = si->srcRegIdx(idx);
+ assert(reg.isMiscReg());
+ return thread->readMiscReg(reg.index());
}
void setMiscRegOperand(const StaticInst *si, int idx,
const MiscReg &val) override
{
- RegId reg = si->destRegIdx(idx);
- assert(reg.regClass == MiscRegClass);
- return this->setMiscReg(reg.regIdx, val);
+ const RegId& reg = si->destRegIdx(idx);
+ assert(reg.isMiscReg());
+ return this->setMiscReg(reg.index(), val);
}
#if THE_ISA == MIPS_ISA
- MiscReg readRegOtherThread(RegId misc_reg, ThreadID tid) override
+ MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid) override
{
panic("MIPS MT not defined for CheckerCPU.\n");
return 0;
}
- void setRegOtherThread(RegId misc_reg, MiscReg val, ThreadID tid) override
+ void setRegOtherThread(const RegId& misc_reg, MiscReg val,
+ ThreadID tid) override
{
panic("MIPS MT not defined for CheckerCPU.\n");
}
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 47a088aa6..0c90590c7 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -595,40 +595,40 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
// We've already popped one dest off the queue,
// so do the fix-up then start with the next dest reg;
if (start_idx >= 0) {
- RegId idx = inst->destRegIdx(start_idx);
- switch (idx.regClass) {
+ const RegId& idx = inst->destRegIdx(start_idx);
+ switch (idx.classValue()) {
case IntRegClass:
- thread->setIntReg(idx.regIdx, mismatch_val);
+ thread->setIntReg(idx.index(), mismatch_val);
break;
case FloatRegClass:
- thread->setFloatRegBits(idx.regIdx, mismatch_val);
+ thread->setFloatRegBits(idx.index(), mismatch_val);
break;
case CCRegClass:
- thread->setCCReg(idx.regIdx, mismatch_val);
+ thread->setCCReg(idx.index(), mismatch_val);
break;
case MiscRegClass:
- thread->setMiscReg(idx.regIdx, mismatch_val);
+ thread->setMiscReg(idx.index(), mismatch_val);
break;
}
}
start_idx++;
uint64_t res = 0;
for (int i = start_idx; i < inst->numDestRegs(); i++) {
- RegId idx = inst->destRegIdx(i);
+ const RegId& idx = inst->destRegIdx(i);
inst->template popResult<uint64_t>(res);
- switch (idx.regClass) {
+ switch (idx.classValue()) {
case IntRegClass:
- thread->setIntReg(idx.regIdx, res);
+ thread->setIntReg(idx.index(), res);
break;
case FloatRegClass:
- thread->setFloatRegBits(idx.regIdx, res);
+ thread->setFloatRegBits(idx.index(), res);
break;
case CCRegClass:
- thread->setCCReg(idx.regIdx, res);
+ thread->setCCReg(idx.index(), res);
break;
case MiscRegClass:
// Try to get the proper misc register index for ARM here...
- thread->setMiscReg(idx.regIdx, res);
+ thread->setMiscReg(idx.index(), res);
break;
// else Register is out of range...
}
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 7b09dde90..e48f5936b 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -301,10 +301,9 @@ class CheckerThreadContext : public ThreadContext
actualTC->setMiscReg(misc_reg, val);
}
- int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); }
- int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); }
- int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); }
- int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); }
+ RegId flattenRegId(const RegId& regId) const {
+ return actualTC->flattenRegId(regId);
+ }
unsigned readStCondFailures()
{ return actualTC->readStCondFailures(); }
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 21:08:26 +0000