2 files changed, 21 insertions, 20 deletions

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 336cb1714..454f3892b 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -47,9 +47,12 @@
 
 // forward declarations
 #if FULL_SYSTEM
+namespace TheISA
+{
+    class ITB;
+    class DTB;
+}
 class Processor;
-class AlphaITB;
-class AlphaDTB;
 class PhysicalMemory;
 
 class RemoteGDB;
@@ -96,8 +99,8 @@ class CheckerCPU : public BaseCPU
     struct Params : public BaseCPU::Params
     {
 #if FULL_SYSTEM
-        AlphaITB *itb;
-        AlphaDTB *dtb;
+        TheISA::ITB *itb;
+        TheISA::DTB *dtb;
 #else
         Process *process;
 #endif
@@ -136,8 +139,8 @@ class CheckerCPU : public BaseCPU
 
     ThreadContext *tc;
 
-    AlphaITB *itb;
-    AlphaDTB *dtb;
+    TheISA::ITB *itb;
+    TheISA::DTB *dtb;
 
 #if FULL_SYSTEM
     Addr dbg_vtophys(Addr addr);
@@ -297,19 +300,19 @@ class CheckerCPU : public BaseCPU
         return thread->readMiscReg(misc_reg);
     }
 
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+    MiscReg readMiscRegWithEffect(int misc_reg)
     {
-        return thread->readMiscRegWithEffect(misc_reg, fault);
+        return thread->readMiscRegWithEffect(misc_reg);
     }
 
-    Fault setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
         result.integer = val;
         miscRegIdxs.push(misc_reg);
         return thread->setMiscReg(misc_reg, val);
     }
 
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
         miscRegIdxs.push(misc_reg);
         return thread->setMiscRegWithEffect(misc_reg, val);
@@ -324,8 +327,6 @@ class CheckerCPU : public BaseCPU
 
 #if FULL_SYSTEM
     Fault hwrei() { return thread->hwrei(); }
-    int readIntrFlag() { return thread->readIntrFlag(); }
-    void setIntrFlag(int val) { thread->setIntrFlag(val); }
     bool inPalMode() { return thread->inPalMode(); }
     void ev5_trap(Fault fault) { fault->invoke(tc); }
     bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index b2806d40b..cd399dd22 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -87,9 +87,9 @@ class CheckerThreadContext : public ThreadContext
 
     PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
 
-    AlphaITB *getITBPtr() { return actualTC->getITBPtr(); }
+    TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
 
-    AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); }
+    TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
 
     Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
 
@@ -248,19 +248,19 @@ class CheckerThreadContext : public ThreadContext
     MiscReg readMiscReg(int misc_reg)
     { return actualTC->readMiscReg(misc_reg); }
 
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
-    { return actualTC->readMiscRegWithEffect(misc_reg, fault); }
+    MiscReg readMiscRegWithEffect(int misc_reg)
+    { return actualTC->readMiscRegWithEffect(misc_reg); }
 
-    Fault setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
         checkerTC->setMiscReg(misc_reg, val);
-        return actualTC->setMiscReg(misc_reg, val);
+        actualTC->setMiscReg(misc_reg, val);
     }
 
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
         checkerTC->setMiscRegWithEffect(misc_reg, val);
-        return actualTC->setMiscRegWithEffect(misc_reg, val);
+        actualTC->setMiscRegWithEffect(misc_reg, val);
     }
 
     unsigned readStCondFailures()