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-rw-r--r--src/cpu/checker/cpu.cc118
-rw-r--r--src/cpu/checker/cpu.hh54
-rw-r--r--src/cpu/checker/thread_context.hh25
3 files changed, 102 insertions, 95 deletions
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 7ae7047e8..2d2f67e6b 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -33,7 +33,7 @@
#include "cpu/base.hh"
#include "cpu/base_dyn_inst.hh"
#include "cpu/checker/cpu.hh"
-#include "cpu/cpu_exec_context.hh"
+#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "cpu/static_inst.hh"
#include "sim/byteswap.hh"
@@ -62,7 +62,7 @@ CheckerCPU::init()
}
CheckerCPU::CheckerCPU(Params *p)
- : BaseCPU(p), cpuXC(NULL), tc(NULL)
+ : BaseCPU(p), thread(NULL), tc(NULL)
{
memReq = NULL;
@@ -94,21 +94,21 @@ CheckerCPU::setMemory(MemObject *mem)
{
memPtr = mem;
#if !FULL_SYSTEM
- cpuXC = new CPUExecContext(this, /* thread_num */ 0, process,
- /* asid */ 0, mem);
+ thread = new SimpleThread(this, /* thread_num */ 0, process,
+ /* asid */ 0, mem);
- cpuXC->setStatus(ThreadContext::Suspended);
- tc = cpuXC->getTC();
+ thread->setStatus(ThreadContext::Suspended);
+ tc = thread->getTC();
threadContexts.push_back(tc);
#else
if (systemPtr) {
- cpuXC = new CPUExecContext(this, 0, systemPtr, itb, dtb, memPtr, false);
+ thread = new SimpleThread(this, 0, systemPtr, itb, dtb, memPtr, false);
- cpuXC->setStatus(ThreadContext::Suspended);
- tc = cpuXC->getTC();
+ thread->setStatus(ThreadContext::Suspended);
+ tc = thread->getTC();
threadContexts.push_back(tc);
- delete cpuXC->kernelStats;
- cpuXC->kernelStats = NULL;
+ delete thread->kernelStats;
+ thread->kernelStats = NULL;
}
#endif
}
@@ -120,13 +120,13 @@ CheckerCPU::setSystem(System *system)
systemPtr = system;
if (memPtr) {
- cpuXC = new CPUExecContext(this, 0, systemPtr, itb, dtb, memPtr, false);
+ thread = new SimpleThread(this, 0, systemPtr, itb, dtb, memPtr, false);
- cpuXC->setStatus(ThreadContext::Suspended);
- tc = cpuXC->getTC();
+ thread->setStatus(ThreadContext::Suspended);
+ tc = thread->getTC();
threadContexts.push_back(tc);
- delete cpuXC->kernelStats;
- cpuXC->kernelStats = NULL;
+ delete thread->kernelStats;
+ thread->kernelStats = NULL;
}
}
#endif
@@ -150,7 +150,7 @@ CheckerCPU::serialize(ostream &os)
BaseCPU::serialize(os);
SERIALIZE_SCALAR(inst);
nameOut(os, csprintf("%s.xc", name()));
- cpuXC->serialize(os);
+ thread->serialize(os);
cacheCompletionEvent.serialize(os);
*/
}
@@ -161,7 +161,7 @@ CheckerCPU::unserialize(Checkpoint *cp, const string &section)
/*
BaseCPU::unserialize(cp, section);
UNSERIALIZE_SCALAR(inst);
- cpuXC->unserialize(cp, csprintf("%s.xc", section));
+ thread->unserialize(cp, csprintf("%s.xc", section));
*/
}
@@ -184,7 +184,7 @@ CheckerCPU::read(Addr addr, T &data, unsigned flags)
// need to fill in CPU & thread IDs here
memReq = new Request();
- memReq->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC());
+ memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
// translate to physical address
translateDataReadReq(memReq);
@@ -254,10 +254,10 @@ CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
// need to fill in CPU & thread IDs here
memReq = new Request();
- memReq->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC());
+ memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
// translate to physical address
- cpuXC->translateDataWriteReq(memReq);
+ thread->translateDataWriteReq(memReq);
// Can compare the write data and result only if it's cacheable,
// not a store conditional, or is a store conditional that
@@ -356,9 +356,9 @@ bool
CheckerCPU::translateInstReq(Request *req)
{
#if FULL_SYSTEM
- return (cpuXC->translateInstReq(req) == NoFault);
+ return (thread->translateInstReq(req) == NoFault);
#else
- cpuXC->translateInstReq(req);
+ thread->translateInstReq(req);
return true;
#endif
}
@@ -366,7 +366,7 @@ CheckerCPU::translateInstReq(Request *req)
void
CheckerCPU::translateDataReadReq(Request *req)
{
- cpuXC->translateDataReadReq(req);
+ thread->translateDataReadReq(req);
if (req->getVaddr() != unverifiedReq->getVaddr()) {
warn("%lli: Request virtual addresses do not match! Inst: %#x, "
@@ -386,7 +386,7 @@ CheckerCPU::translateDataReadReq(Request *req)
void
CheckerCPU::translateDataWriteReq(Request *req)
{
- cpuXC->translateDataWriteReq(req);
+ thread->translateDataWriteReq(req);
if (req->getVaddr() != unverifiedReq->getVaddr()) {
warn("%lli: Request virtual addresses do not match! Inst: %#x, "
@@ -475,9 +475,9 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
Fault fault = NoFault;
// maintain $r0 semantics
- cpuXC->setIntReg(ZeroReg, 0);
+ thread->setIntReg(ZeroReg, 0);
#ifdef TARGET_ALPHA
- cpuXC->setFloatRegDouble(ZeroReg, 0.0);
+ thread->setFloatRegDouble(ZeroReg, 0.0);
#endif // TARGET_ALPHA
// Check if any recent PC changes match up with anything we
@@ -485,14 +485,14 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
// PC-based events have occurred in both the checker and CPU.
if (changedPC) {
DPRINTF(Checker, "Changed PC recently to %#x\n",
- cpuXC->readPC());
+ thread->readPC());
if (willChangePC) {
- if (newPC == cpuXC->readPC()) {
+ if (newPC == thread->readPC()) {
DPRINTF(Checker, "Changed PC matches expected PC\n");
} else {
warn("%lli: Changed PC does not match expected PC, "
"changed: %#x, expected: %#x",
- curTick, cpuXC->readPC(), newPC);
+ curTick, thread->readPC(), newPC);
handleError();
}
willChangePC = false;
@@ -501,7 +501,7 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
}
if (changedNextPC) {
DPRINTF(Checker, "Changed NextPC recently to %#x\n",
- cpuXC->readNextPC());
+ thread->readNextPC());
changedNextPC = false;
}
@@ -513,13 +513,13 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
#define IFETCH_FLAGS(pc) 0
#endif
- uint64_t fetch_PC = cpuXC->readPC() & ~3;
+ uint64_t fetch_PC = thread->readPC() & ~3;
// set up memory request for instruction fetch
memReq = new Request(inst->threadNumber, fetch_PC,
sizeof(uint32_t),
- IFETCH_FLAGS(cpuXC->readPC()),
- fetch_PC, cpuXC->readCpuId(), inst->threadNumber);
+ IFETCH_FLAGS(thread->readPC()),
+ fetch_PC, thread->readCpuId(), inst->threadNumber);
bool succeeded = translateInstReq(memReq);
@@ -531,12 +531,12 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
// translate this instruction; in the SMT case it's
// possible that its ITB entry was kicked out.
warn("%lli: Instruction PC %#x was not found in the ITB!",
- curTick, cpuXC->readPC());
+ curTick, thread->readPC());
handleError();
// go to the next instruction
- cpuXC->setPC(cpuXC->readNextPC());
- cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
+ thread->setPC(thread->readNextPC());
+ thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
return;
} else {
@@ -567,10 +567,10 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
validateInst(inst);
curStaticInst = StaticInst::decode(makeExtMI(machInst,
- cpuXC->readPC()));
+ thread->readPC()));
#if FULL_SYSTEM
- cpuXC->setInst(machInst);
+ thread->setInst(machInst);
#endif // FULL_SYSTEM
fault = inst->getFault();
@@ -585,7 +585,7 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
// that the instruction is properly marked as a fault.
if (fault == NoFault) {
- cpuXC->func_exe_inst++;
+ thread->funcExeInst++;
fault = curStaticInst->execute(this, NULL);
@@ -601,21 +601,21 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
#if FULL_SYSTEM
fault->invoke(xcProxy);
willChangePC = true;
- newPC = cpuXC->readPC();
+ newPC = thread->readPC();
DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
#else // !FULL_SYSTEM
- fatal("fault (%d) detected @ PC 0x%08p", fault, cpuXC->readPC());
+ fatal("fault (%d) detected @ PC 0x%08p", fault, thread->readPC());
#endif // FULL_SYSTEM
} else {
#if THE_ISA != MIPS_ISA
// go to the next instruction
- cpuXC->setPC(cpuXC->readNextPC());
- cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
+ thread->setPC(thread->readNextPC());
+ thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
#else
// go to the next instruction
- cpuXC->setPC(cpuXC->readNextPC());
- cpuXC->setNextPC(cpuXC->readNextNPC());
- cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst));
+ thread->setPC(thread->readNextPC());
+ thread->setNextPC(thread->readNextNPC());
+ thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
#endif
}
@@ -627,13 +627,13 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
Addr oldpc;
int count = 0;
do {
- oldpc = cpuXC->readPC();
+ oldpc = thread->readPC();
system->pcEventQueue.service(xcProxy);
count++;
- } while (oldpc != cpuXC->readPC());
+ } while (oldpc != thread->readPC());
if (count > 1) {
willChangePC = true;
- newPC = cpuXC->readPC();
+ newPC = thread->readPC();
DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
}
#endif
@@ -677,9 +677,9 @@ template <class DynInstPtr>
void
Checker<DynInstPtr>::validateInst(DynInstPtr &inst)
{
- if (inst->readPC() != cpuXC->readPC()) {
+ if (inst->readPC() != thread->readPC()) {
warn("%lli: PCs do not match! Inst: %#x, checker: %#x",
- curTick, inst->readPC(), cpuXC->readPC());
+ curTick, inst->readPC(), thread->readPC());
if (changedPC) {
warn("%lli: Changed PCs recently, may not be an error",
curTick);
@@ -710,11 +710,11 @@ Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
// instruction and write it to the register.
RegIndex idx = inst->destRegIdx(0);
if (idx < TheISA::FP_Base_DepTag) {
- cpuXC->setIntReg(idx, inst->readIntResult());
+ thread->setIntReg(idx, inst->readIntResult());
} else if (idx < TheISA::Fpcr_DepTag) {
- cpuXC->setFloatRegBits(idx, inst->readIntResult());
+ thread->setFloatRegBits(idx, inst->readIntResult());
} else {
- cpuXC->setMiscReg(idx, inst->readIntResult());
+ thread->setMiscReg(idx, inst->readIntResult());
}
} else if (result.integer != inst->readIntResult()) {
warn("%lli: Instruction results do not match! (Values may not "
@@ -724,10 +724,10 @@ Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
}
}
- if (inst->readNextPC() != cpuXC->readNextPC()) {
+ if (inst->readNextPC() != thread->readNextPC()) {
warn("%lli: Instruction next PCs do not match! Inst: %#x, "
"checker: %#x",
- curTick, inst->readNextPC(), cpuXC->readNextPC());
+ curTick, inst->readNextPC(), thread->readNextPC());
handleError();
}
@@ -741,12 +741,12 @@ Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
miscRegIdxs.pop();
if (inst->tcBase()->readMiscReg(misc_reg_idx) !=
- cpuXC->readMiscReg(misc_reg_idx)) {
+ thread->readMiscReg(misc_reg_idx)) {
warn("%lli: Misc reg idx %i (side effect) does not match! "
"Inst: %#x, checker: %#x",
curTick, misc_reg_idx,
inst->tcBase()->readMiscReg(misc_reg_idx),
- cpuXC->readMiscReg(misc_reg_idx));
+ thread->readMiscReg(misc_reg_idx));
handleError();
}
}
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 484f4cf04..f733becd4 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -38,7 +38,7 @@
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/base_dyn_inst.hh"
-#include "cpu/cpu_exec_context.hh"
+#include "cpu/simple_thread.hh"
#include "cpu/pc_event.hh"
#include "cpu/static_inst.hh"
#include "sim/eventq.hh"
@@ -77,7 +77,7 @@ class Sampler;
* instructions marked as "IsUnverifiable", the checker assumes that
* the value from the main CPU's execution is correct and simply
* copies that value. It provides a CheckerThreadContext (see
- * checker/exec_context.hh) that provides hooks for updating the
+ * checker/thread_context.hh) that provides hooks for updating the
* Checker's state through any ThreadContext accesses. This allows the
* checker to be able to correctly verify instructions, even with
* external accesses to the ThreadContext that change state.
@@ -129,8 +129,8 @@ class CheckerCPU : public BaseCPU
Port *dcachePort;
public:
- // execution context
- CPUExecContext *cpuXC;
+ // Primary thread being run.
+ SimpleThread *thread;
ThreadContext *tc;
@@ -213,43 +213,43 @@ class CheckerCPU : public BaseCPU
uint64_t readIntReg(const StaticInst *si, int idx)
{
- return cpuXC->readIntReg(si->srcRegIdx(idx));
+ return thread->readIntReg(si->srcRegIdx(idx));
}
FloatReg readFloatReg(const StaticInst *si, int idx, int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
- return cpuXC->readFloatReg(reg_idx, width);
+ return thread->readFloatReg(reg_idx, width);
}
FloatReg readFloatReg(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
- return cpuXC->readFloatReg(reg_idx);
+ return thread->readFloatReg(reg_idx);
}
FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
- return cpuXC->readFloatRegBits(reg_idx, width);
+ return thread->readFloatRegBits(reg_idx, width);
}
FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
- return cpuXC->readFloatRegBits(reg_idx);
+ return thread->readFloatRegBits(reg_idx);
}
void setIntReg(const StaticInst *si, int idx, uint64_t val)
{
- cpuXC->setIntReg(si->destRegIdx(idx), val);
+ thread->setIntReg(si->destRegIdx(idx), val);
result.integer = val;
}
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
- cpuXC->setFloatReg(reg_idx, val, width);
+ thread->setFloatReg(reg_idx, val, width);
switch(width) {
case 32:
result.fp = val;
@@ -263,7 +263,7 @@ class CheckerCPU : public BaseCPU
void setFloatReg(const StaticInst *si, int idx, FloatReg val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
- cpuXC->setFloatReg(reg_idx, val);
+ thread->setFloatReg(reg_idx, val);
result.fp = val;
}
@@ -271,46 +271,46 @@ class CheckerCPU : public BaseCPU
int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
- cpuXC->setFloatRegBits(reg_idx, val, width);
+ thread->setFloatRegBits(reg_idx, val, width);
result.integer = val;
}
void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
- cpuXC->setFloatRegBits(reg_idx, val);
+ thread->setFloatRegBits(reg_idx, val);
result.integer = val;
}
- uint64_t readPC() { return cpuXC->readPC(); }
+ uint64_t readPC() { return thread->readPC(); }
- uint64_t readNextPC() { return cpuXC->readNextPC(); }
+ uint64_t readNextPC() { return thread->readNextPC(); }
void setNextPC(uint64_t val) {
- cpuXC->setNextPC(val);
+ thread->setNextPC(val);
}
MiscReg readMiscReg(int misc_reg)
{
- return cpuXC->readMiscReg(misc_reg);
+ return thread->readMiscReg(misc_reg);
}
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
{
- return cpuXC->readMiscRegWithEffect(misc_reg, fault);
+ return thread->readMiscRegWithEffect(misc_reg, fault);
}
Fault setMiscReg(int misc_reg, const MiscReg &val)
{
result.integer = val;
miscRegIdxs.push(misc_reg);
- return cpuXC->setMiscReg(misc_reg, val);
+ return thread->setMiscReg(misc_reg, val);
}
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
miscRegIdxs.push(misc_reg);
- return cpuXC->setMiscRegWithEffect(misc_reg, val);
+ return thread->setMiscRegWithEffect(misc_reg, val);
}
void recordPCChange(uint64_t val) { changedPC = true; }
@@ -321,12 +321,12 @@ class CheckerCPU : public BaseCPU
void translateDataReadReq(Request *req);
#if FULL_SYSTEM
- Fault hwrei() { return cpuXC->hwrei(); }
- int readIntrFlag() { return cpuXC->readIntrFlag(); }
- void setIntrFlag(int val) { cpuXC->setIntrFlag(val); }
- bool inPalMode() { return cpuXC->inPalMode(); }
+ Fault hwrei() { return thread->hwrei(); }
+ int readIntrFlag() { return thread->readIntrFlag(); }
+ void setIntrFlag(int val) { thread->setIntrFlag(val); }
+ bool inPalMode() { return thread->inPalMode(); }
void ev5_trap(Fault fault) { fault->invoke(xcProxy); }
- bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); }
+ bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
#else
// Assume that the normal CPU's call to syscall was successful.
// The checker's state would have already been updated by the syscall.
@@ -341,7 +341,7 @@ class CheckerCPU : public BaseCPU
bool checkFlags(Request *req);
ThreadContext *tcBase() { return tc; }
- CPUExecContext *cpuXCBase() { return cpuXC; }
+ SimpleThread *threadBase() { return thread; }
Result unverifiedResult;
Request *unverifiedReq;
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 48890584d..d3eb9cf0c 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -26,11 +26,11 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_CHECKER_EXEC_CONTEXT_HH__
-#define __CPU_CHECKER_EXEC_CONTEXT_HH__
+#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
+#define __CPU_CHECKER_THREAD_CONTEXT_HH__
#include "cpu/checker/cpu.hh"
-#include "cpu/cpu_exec_context.hh"
+#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
class EndQuiesceEvent;
@@ -41,23 +41,30 @@ namespace Kernel {
/**
* Derived ThreadContext class for use with the Checker. The template
* parameter is the ThreadContext class used by the specific CPU being
- * verified. This CheckerThreadContext is then used by the main CPU in
- * place of its usual ThreadContext class. It handles updating the
- * checker's state any time state is updated through the ThreadContext.
+ * verified. This CheckerThreadContext is then used by the main CPU
+ * in place of its usual ThreadContext class. It handles updating the
+ * checker's state any time state is updated externally through the
+ * ThreadContext.
*/
template <class TC>
class CheckerThreadContext : public ThreadContext
{
public:
CheckerThreadContext(TC *actual_tc,
- CheckerCPU *checker_cpu)
- : actualTC(actual_tc), checkerTC(checker_cpu->cpuXC),
+ CheckerCPU *checker_cpu)
+ : actualTC(actual_tc), checkerTC(checker_cpu->thread),
checkerCPU(checker_cpu)
{ }
private:
+ /** The main CPU's ThreadContext, or class that implements the
+ * ThreadContext interface. */
TC *actualTC;
- CPUExecContext *checkerTC;
+ /** The checker's own SimpleThread. Will be updated any time
+ * anything uses this ThreadContext to externally update a
+ * thread's state. */
+ SimpleThread *checkerTC;
+ /** Pointer to the checker CPU. */
CheckerCPU *checkerCPU;
public:
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 17:59:55 +0000