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-rw-r--r--src/cpu/checker/cpu.hh7
-rw-r--r--src/cpu/checker/thread_context.hh4
2 files changed, 5 insertions, 6 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 2c7e022bd..4468689bd 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -417,7 +417,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
}
void
- setMiscRegNoEffect(int misc_reg, const RegVal &val)
+ setMiscRegNoEffect(int misc_reg, RegVal val)
{
DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n",
misc_reg);
@@ -426,7 +426,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
}
void
- setMiscReg(int misc_reg, const RegVal &val) override
+ setMiscReg(int misc_reg, RegVal val) override
{
DPRINTF(Checker, "Setting misc reg %d with effect to check later\n",
misc_reg);
@@ -443,8 +443,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
}
void
- setMiscRegOperand(const StaticInst *si, int idx,
- const RegVal &val) override
+ setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 854771fdd..b5a2079ea 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -348,7 +348,7 @@ class CheckerThreadContext : public ThreadContext
{ return actualTC->readMiscReg(misc_reg); }
void
- setMiscRegNoEffect(int misc_reg, const RegVal &val)
+ setMiscRegNoEffect(int misc_reg, RegVal val)
{
DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
" and O3..\n", misc_reg);
@@ -357,7 +357,7 @@ class CheckerThreadContext : public ThreadContext
}
void
- setMiscReg(int misc_reg, const RegVal &val)
+ setMiscReg(int misc_reg, RegVal val)
{
DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
" and O3..\n", misc_reg);