diff options
Diffstat (limited to 'src/cpu/exec_context.hh')
| -rw-r--r-- | src/cpu/exec_context.hh | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index 75f428b87..87af91623 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, 2016 ARM Limited + * Copyright (c) 2014, 2016-2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -77,6 +77,7 @@ class ExecContext { typedef TheISA::CCReg CCReg; using VecRegContainer = TheISA::VecRegContainer; using VecElem = TheISA::VecElem; + using VecPredRegContainer = TheISA::VecPredRegContainer; public: /** @@ -168,6 +169,22 @@ class ExecContext { const VecElem val) = 0; /** @} */ + /** Predicate registers interface. */ + /** @{ */ + /** Reads source predicate register operand. */ + virtual const VecPredRegContainer& + readVecPredRegOperand(const StaticInst *si, int idx) const = 0; + + /** Gets destination predicate register operand for modification. */ + virtual VecPredRegContainer& + getWritableVecPredRegOperand(const StaticInst *si, int idx) = 0; + + /** Sets a destination predicate register operand to a value. */ + virtual void + setVecPredRegOperand(const StaticInst *si, int idx, + const VecPredRegContainer& val) = 0; + /** @} */ + /** * @{ * @name Condition Code Registers |