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Diffstat (limited to 'src/cpu/inorder/InOrderCPU.py')
| -rw-r--r-- | src/cpu/inorder/InOrderCPU.py | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py index 40af48b19..2dcd51d45 100644 --- a/src/cpu/inorder/InOrderCPU.py +++ b/src/cpu/inorder/InOrderCPU.py @@ -42,9 +42,6 @@ class InOrderCPU(BaseCPU): cachePorts = Param.Unsigned(2, "Cache Ports") stageWidth = Param.Unsigned(4, "Stage width") - fetchMemPort = Param.String("icache_port" , "Name of Memory Port to get instructions from") - dataMemPort = Param.String("dcache_port" , "Name of Memory Port to get data from") - fetchBuffSize = Param.Unsigned(4, "Fetch Buffer Size (Number of Cache Blocks Stored)") memBlockSize = Param.Unsigned(64, "Memory Block Size") |