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Diffstat (limited to 'src/cpu/inorder/InOrderCPU.py')
| -rw-r--r-- | src/cpu/inorder/InOrderCPU.py | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py index 416b18dd3..119de7f1c 100644 --- a/src/cpu/inorder/InOrderCPU.py +++ b/src/cpu/inorder/InOrderCPU.py @@ -65,13 +65,13 @@ class InOrderCPU(BaseCPU): stageTracing = Param.Bool(False, "Enable tracing of each stage in CPU") - multLatency = Param.Unsigned(1, "Latency for Multiply Operations") - multRepeatRate = Param.Unsigned(1, "Repeat Rate for Multiply Operations") - div8Latency = Param.Unsigned(1, "Latency for 8-bit Divide Operations") - div8RepeatRate = Param.Unsigned(1, "Repeat Rate for 8-bit Divide Operations") - div16Latency = Param.Unsigned(1, "Latency for 16-bit Divide Operations") - div16RepeatRate = Param.Unsigned(1, "Repeat Rate for 16-bit Divide Operations") - div24Latency = Param.Unsigned(1, "Latency for 24-bit Divide Operations") - div24RepeatRate = Param.Unsigned(1, "Repeat Rate for 24-bit Divide Operations") - div32Latency = Param.Unsigned(1, "Latency for 32-bit Divide Operations") - div32RepeatRate = Param.Unsigned(1, "Repeat Rate for 32-bit Divide Operations") + multLatency = Param.Cycles(1, "Latency for Multiply Operations") + multRepeatRate = Param.Cycles(1, "Repeat Rate for Multiply Operations") + div8Latency = Param.Cycles(1, "Latency for 8-bit Divide Operations") + div8RepeatRate = Param.Cycles(1, "Repeat Rate for 8-bit Divide Operations") + div16Latency = Param.Cycles(1, "Latency for 16-bit Divide Operations") + div16RepeatRate = Param.Cycles(1, "Repeat Rate for 16-bit Divide Operations") + div24Latency = Param.Cycles(1, "Latency for 24-bit Divide Operations") + div24RepeatRate = Param.Cycles(1, "Repeat Rate for 24-bit Divide Operations") + div32Latency = Param.Cycles(1, "Latency for 32-bit Divide Operations") + div32RepeatRate = Param.Cycles(1, "Repeat Rate for 32-bit Divide Operations") |