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-rw-r--r--src/cpu/inorder/InOrderCPU.py4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py
index 4caf254c4..920b9cdc1 100644
--- a/src/cpu/inorder/InOrderCPU.py
+++ b/src/cpu/inorder/InOrderCPU.py
@@ -47,6 +47,10 @@ class InOrderCPU(BaseCPU):
def require_caches(cls):
return True
+ @classmethod
+ def support_take_over(cls):
+ return True
+
threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)")
cachePorts = Param.Unsigned(2, "Cache Ports")