summaryrefslogtreecommitdiff
path: root/src/cpu/inorder/cpu.cc
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/inorder/cpu.cc')
-rw-r--r--src/cpu/inorder/cpu.cc133
1 files changed, 59 insertions, 74 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 232554db2..010bdb512 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -33,7 +33,6 @@
#include "arch/utility.hh"
#include "base/bigint.hh"
-#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "cpu/inorder/resources/resource_list.hh"
#include "cpu/inorder/cpu.hh"
@@ -46,22 +45,21 @@
#include "cpu/activity.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
+#include "cpu/quiesce_event.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "debug/Activity.hh"
#include "debug/InOrderCPU.hh"
+#include "debug/Interrupt.hh"
#include "debug/RefCount.hh"
#include "debug/SkedCache.hh"
#include "debug/Quiesce.hh"
#include "mem/translating_port.hh"
#include "params/InOrderCPU.hh"
+#include "sim/full_system.hh"
#include "sim/process.hh"
#include "sim/stat_control.hh"
-
-#if FULL_SYSTEM
-#include "cpu/quiesce_event.hh"
#include "sim/system.hh"
-#endif
#if THE_ISA == ALPHA_ISA
#include "arch/alpha/osfpal.hh"
@@ -153,12 +151,11 @@ InOrderCPU::CPUEvent::process()
cpu->trapPending[tid] = false;
break;
-#if !FULL_SYSTEM
case Syscall:
cpu->syscall(inst->syscallNum, tid);
cpu->resPool->trap(fault, tid, inst);
break;
-#endif
+
default:
fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
}
@@ -198,9 +195,7 @@ InOrderCPU::InOrderCPU(Params *params)
timeBuffer(2 , 2),
removeInstsThisCycle(false),
activityRec(params->name, NumStages, 10, params->activity),
-#if FULL_SYSTEM
system(params->system),
-#endif // FULL_SYSTEM
#ifdef DEBUG
cpuEventNum(0),
resReqCount(0),
@@ -218,33 +213,33 @@ InOrderCPU::InOrderCPU(Params *params)
// Resize for Multithreading CPUs
thread.resize(numThreads);
-#if !FULL_SYSTEM
ThreadID active_threads = params->workload.size();
+ if (FullSystem) {
+ active_threads = 1;
+ } else {
+ active_threads = params->workload.size();
- if (active_threads > MaxThreads) {
- panic("Workload Size too large. Increase the 'MaxThreads'"
- "in your InOrder implementation or "
- "edit your workload size.");
- }
+ if (active_threads > MaxThreads) {
+ panic("Workload Size too large. Increase the 'MaxThreads'"
+ "in your InOrder implementation or "
+ "edit your workload size.");
+ }
-
- if (active_threads > 1) {
- threadModel = (InOrderCPU::ThreadModel) params->threadModel;
-
- if (threadModel == SMT) {
- DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
- } else if (threadModel == SwitchOnCacheMiss) {
- DPRINTF(InOrderCPU, "Setting Thread Model to "
- "Switch On Cache Miss\n");
+
+ if (active_threads > 1) {
+ threadModel = (InOrderCPU::ThreadModel) params->threadModel;
+
+ if (threadModel == SMT) {
+ DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
+ } else if (threadModel == SwitchOnCacheMiss) {
+ DPRINTF(InOrderCPU, "Setting Thread Model to "
+ "Switch On Cache Miss\n");
+ }
+
+ } else {
+ threadModel = Single;
}
-
- } else {
- threadModel = Single;
}
-
-
-
-#endif
// Bind the fetch & data ports from the resource pool.
fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
@@ -261,36 +256,34 @@ InOrderCPU::InOrderCPU(Params *params)
pc[tid].set(0);
lastCommittedPC[tid].set(0);
-#if FULL_SYSTEM
- // SMT is not supported in FS mode yet.
- assert(numThreads == 1);
- thread[tid] = new Thread(this, 0);
-#else
- if (tid < (ThreadID)params->workload.size()) {
- DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
- tid, params->workload[tid]->prog_fname);
- thread[tid] =
- new Thread(this, tid, params->workload[tid]);
+ if (FullSystem) {
+ // SMT is not supported in FS mode yet.
+ assert(numThreads == 1);
+ thread[tid] = new Thread(this, 0, NULL);
} else {
- //Allocate Empty thread so M5 can use later
- //when scheduling threads to CPU
- Process* dummy_proc = params->workload[0];
- thread[tid] = new Thread(this, tid, dummy_proc);
+ if (tid < (ThreadID)params->workload.size()) {
+ DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
+ tid, params->workload[tid]->prog_fname);
+ thread[tid] =
+ new Thread(this, tid, params->workload[tid]);
+ } else {
+ //Allocate Empty thread so M5 can use later
+ //when scheduling threads to CPU
+ Process* dummy_proc = params->workload[0];
+ thread[tid] = new Thread(this, tid, dummy_proc);
+ }
+
+ // Eventually set this with parameters...
+ asid[tid] = tid;
}
-
- // Eventually set this with parameters...
- asid[tid] = tid;
-#endif
// Setup the TC that will serve as the interface to the threads/CPU.
InOrderThreadContext *tc = new InOrderThreadContext;
tc->cpu = this;
tc->thread = thread[tid];
-#if FULL_SYSTEM
// Setup quiesce event.
this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
-#endif
// Give the thread the TC.
thread[tid]->tc = tc;
@@ -349,16 +342,17 @@ InOrderCPU::InOrderCPU(Params *params)
dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
-#if FULL_SYSTEM
- // Use this dummy inst to force squashing behind every instruction
- // in pipeline
- dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0);
- dummyTrapInst[tid]->seqNum = 0;
- dummyTrapInst[tid]->squashSeqNum = 0;
- dummyTrapInst[tid]->setTid(tid);
-#endif
- trapPending[tid] = false;
+ if (FullSystem) {
+ // Use this dummy inst to force squashing behind every instruction
+ // in pipeline
+ dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0);
+ dummyTrapInst[tid]->seqNum = 0;
+ dummyTrapInst[tid]->squashSeqNum = 0;
+ dummyTrapInst[tid]->setTid(tid);
+ }
+
+ trapPending[tid] = false;
}
@@ -699,9 +693,7 @@ InOrderCPU::tick()
++numCycles;
-#if FULL_SYSTEM
checkForInterrupts();
-#endif
bool pipes_idle = true;
//Tick each of the stages
@@ -762,12 +754,12 @@ InOrderCPU::init()
for (ThreadID tid = 0; tid < numThreads; ++tid)
thread[tid]->inSyscall = true;
-#if FULL_SYSTEM
- for (ThreadID tid = 0; tid < numThreads; tid++) {
- ThreadContext *src_tc = threadContexts[tid];
- TheISA::initCPU(src_tc, src_tc->contextId());
+ if (FullSystem) {
+ for (ThreadID tid = 0; tid < numThreads; tid++) {
+ ThreadContext *src_tc = threadContexts[tid];
+ TheISA::initCPU(src_tc, src_tc->contextId());
+ }
}
-#endif
// Clear inSyscall.
for (ThreadID tid = 0; tid < numThreads; ++tid)
@@ -783,7 +775,6 @@ InOrderCPU::getPort(const std::string &if_name, int idx)
return resPool->getPort(if_name, idx);
}
-#if FULL_SYSTEM
Fault
InOrderCPU::hwrei(ThreadID tid)
{
@@ -888,7 +879,6 @@ InOrderCPU::processInterrupts(Fault interrupt)
trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
}
-
void
InOrderCPU::updateMemPorts()
{
@@ -898,7 +888,6 @@ InOrderCPU::updateMemPorts()
for (ThreadID i = 0; i < size; ++i)
thread[i]->connectMemPorts(thread[i]->getTC());
}
-#endif
void
InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
@@ -1690,7 +1679,6 @@ InOrderCPU::wakeCPU()
schedule(&tickEvent, nextCycle(curTick()));
}
-#if FULL_SYSTEM
// Lots of copied full system code...place into BaseCPU class?
void
InOrderCPU::wakeup()
@@ -1703,9 +1691,7 @@ InOrderCPU::wakeup()
DPRINTF(Quiesce, "Suspended Processor woken\n");
threadContexts[0]->activate();
}
-#endif
-#if !FULL_SYSTEM
void
InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
{
@@ -1743,7 +1729,6 @@ InOrderCPU::syscall(int64_t callnum, ThreadID tid)
// Clear Non-Speculative Block Variable
nonSpecInstActive[tid] = false;
}
-#endif
TheISA::TLB*
InOrderCPU::getITBPtr()
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-04 21:45:15 +0000