diff options
Diffstat (limited to 'src/cpu/inorder/cpu.hh')
| -rw-r--r-- | src/cpu/inorder/cpu.hh | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 744dd5cf9..8b2442ac0 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -103,9 +103,6 @@ class InOrderCPU : public BaseCPU Params *cpu_params; - TheISA::TLB * itb; - TheISA::TLB * dtb; - public: enum Status { Running, @@ -236,11 +233,17 @@ class InOrderCPU : public BaseCPU */ unsigned fetchPortIdx; + /** Identifies the resource id that identifies a ITB */ + unsigned itbIdx; + /** Identifies the resource id that identifies a data * access unit. */ unsigned dataPortIdx; + /** Identifies the resource id that identifies a DTB */ + unsigned dtbIdx; + /** The Pipeline Stages for the CPU */ PipelineStage *pipelineStage[ThePipeline::NumStages]; @@ -262,6 +265,9 @@ class InOrderCPU : public BaseCPU /** Communication structure that sits in between pipeline stages */ StageQueue *stageQueue[ThePipeline::NumStages-1]; + TheISA::ITB *getITBPtr(); + TheISA::DTB *getDTBPtr(); + public: /** Registers statistics. */ @@ -308,6 +314,8 @@ class InOrderCPU : public BaseCPU void deallocateThread(unsigned tid); void deactivateThread(unsigned tid); + PipelineStage* getPipeStage(int stage_num); + int contextId() { |