diff options
Diffstat (limited to 'src/cpu/inorder/resources/bpred_unit.cc')
| -rw-r--r-- | src/cpu/inorder/resources/bpred_unit.cc | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/src/cpu/inorder/resources/bpred_unit.cc b/src/cpu/inorder/resources/bpred_unit.cc index 66d0779a2..df6b33792 100644 --- a/src/cpu/inorder/resources/bpred_unit.cc +++ b/src/cpu/inorder/resources/bpred_unit.cc @@ -196,7 +196,7 @@ BPredUnit::predict(DynInstPtr &inst, Addr &PC, unsigned tid) predict_record.RASIndex = RAS[tid].topIdx(); predict_record.RASTarget = target; - assert(predict_record.RASIndex < 16); + assert(predict_record.RASIndex < 16); RAS[tid].pop(); @@ -219,14 +219,14 @@ BPredUnit::predict(DynInstPtr &inst, Addr &PC, unsigned tid) } if (inst->isCall() && - inst->isUncondCtrl() && - inst->isDirectCtrl()) { - target = inst->branchTarget(); + inst->isUncondCtrl() && + inst->isDirectCtrl()) { + target = inst->branchTarget(); DPRINTF(Fetch, "BranchPred: [tid:%i]: Setting %#x predicted" " target to %#x.\n", tid, inst->readPC(), target); - } else if (BTB.valid(PC, tid)) { + } else if (BTB.valid(PC, tid)) { ++BTBHits; // If it's not a return, use the BTB to get the target addr. @@ -248,7 +248,12 @@ BPredUnit::predict(DynInstPtr &inst, Addr &PC, unsigned tid) PC = target; inst->setPredTarg(target); } else { +#if ISA_HAS_DELAY_SLOT + // This value will be inst->PC + 4 (nextPC) + // Delay Slot archs need this to be inst->PC + 8 (nextNPC) + // so we increment one more time here. PC = PC + sizeof(MachInst); +#endif inst->setPredTarg(PC); } |