diff options
Diffstat (limited to 'src/cpu/inorder/resources/graduation_unit.cc')
| -rw-r--r-- | src/cpu/inorder/resources/graduation_unit.cc | 25 |
1 files changed, 7 insertions, 18 deletions
diff --git a/src/cpu/inorder/resources/graduation_unit.cc b/src/cpu/inorder/resources/graduation_unit.cc index 9d19c2eef..8ccdaa36a 100644 --- a/src/cpu/inorder/resources/graduation_unit.cc +++ b/src/cpu/inorder/resources/graduation_unit.cc @@ -51,31 +51,23 @@ GraduationUnit::execute(int slot_num) { ResourceRequest* grad_req = reqMap[slot_num]; DynInstPtr inst = reqMap[slot_num]->inst; - Fault fault = reqMap[slot_num]->fault; ThreadID tid = inst->readTid(); int stage_num = inst->resSched.top()->stageNum; - grad_req->fault = NoFault; - switch (grad_req->cmd) { case GraduateInst: { - // @TODO: Instructions should never really get to this point since - // this should be handled through the request interface. Check to - // make sure this happens and delete this code. - if (lastCycleGrad != curTick()) { - lastCycleGrad = curTick(); - numCycleGrad = 0; - } else if (numCycleGrad > width) { - DPRINTF(InOrderGraduation, - "Graduation bandwidth reached for this cycle.\n"); - return; - } - // Make sure this is the last thing on the resource schedule assert(inst->resSched.size() == 1); + // Handle Any Faults Before Graduating Instruction + if (inst->fault != NoFault) { + cpu->trap(inst->fault, tid, inst); + grad_req->setCompleted(false); + return; + } + DPRINTF(InOrderGraduation, "[tid:%i] Graduating instruction [sn:%i].\n", tid, inst->seqNum); @@ -97,9 +89,6 @@ GraduationUnit::execute(int slot_num) // Tell CPU that instruction is finished processing cpu->instDone(inst, tid); - //cpu->pipelineStage[stage_num]->toPrevStages-> - //stageInfo[stage_num][tid].doneSeqNum = inst->seqNum; - grad_req->done(); } break; |