diff options
Diffstat (limited to 'src/cpu/inorder/resources')
-rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 6 | ||||
-rw-r--r-- | src/cpu/inorder/resources/tlb_unit.cc | 11 | ||||
-rw-r--r-- | src/cpu/inorder/resources/tlb_unit.hh | 5 |
3 files changed, 15 insertions, 7 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 1b5d07450..6fe0bcf76 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -451,10 +451,12 @@ CacheUnit::processCacheCompletion(PacketPtr pkt) // Get resource request info - // @todo: SMT needs to figure out where to get thread # from. - unsigned tid = 0; unsigned stage_num = cache_req->getStageNum(); DynInstPtr inst = cache_req->inst; + unsigned tid; + + + tid = cache_req->inst->readTid(); if (!cache_req->isSquashed()) { if (inst->resSched.top()->cmd == CompleteFetch) { diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc index fbc6bc195..dbf799661 100644 --- a/src/cpu/inorder/resources/tlb_unit.cc +++ b/src/cpu/inorder/resources/tlb_unit.cc @@ -118,7 +118,7 @@ TLBUnit::execute(int slot_idx) { tlb_req->fault = _tlb->translateAtomic(tlb_req->memReq, - cpu->thread[tid]->getTC(), false, true); + cpu->thread[tid]->getTC(), TheISA::TLB::Execute); if (tlb_req->fault != NoFault) { DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating " @@ -142,14 +142,19 @@ TLBUnit::execute(int slot_idx) } break; - case DataLookup: + case DataReadLookup: + case DataWriteLookup: { DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i]: Attempting to translate %08p.\n", tid, seq_num, tlb_req->memReq->getVaddr()); + + TheISA::TLB::Mode tlb_mode = (tlb_req->cmd == DataReadLookup) ? + TheISA::TLB::Read : TheISA::TLB::Write; + tlb_req->fault = _tlb->translateAtomic(tlb_req->memReq, - cpu->thread[tid]->getTC()); + cpu->thread[tid]->getTC(), tlb_mode); if (tlb_req->fault != NoFault) { DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating " diff --git a/src/cpu/inorder/resources/tlb_unit.hh b/src/cpu/inorder/resources/tlb_unit.hh index b53f251fc..b0cdac2a2 100644 --- a/src/cpu/inorder/resources/tlb_unit.hh +++ b/src/cpu/inorder/resources/tlb_unit.hh @@ -47,7 +47,8 @@ class TLBUnit : public InstBuffer { enum TLBCommand { FetchLookup, - DataLookup + DataReadLookup, + DataWriteLookup }; public: @@ -103,7 +104,7 @@ class TLBUnitRequest : public ResourceRequest { if (_cmd == TLBUnit::FetchLookup) { aligned_addr = inst->getMemAddr(); - req_size = sizeof(MachInst); + req_size = sizeof(TheISA::MachInst); flags = 0; } else { aligned_addr = inst->getMemAddr();; |