diff options
Diffstat (limited to 'src/cpu/inorder/resources')
-rw-r--r-- | src/cpu/inorder/resources/bpred_unit.cc | 463 | ||||
-rw-r--r-- | src/cpu/inorder/resources/bpred_unit.hh | 267 | ||||
-rw-r--r-- | src/cpu/inorder/resources/branch_predictor.cc | 25 | ||||
-rw-r--r-- | src/cpu/inorder/resources/branch_predictor.hh | 4 |
4 files changed, 14 insertions, 745 deletions
diff --git a/src/cpu/inorder/resources/bpred_unit.cc b/src/cpu/inorder/resources/bpred_unit.cc deleted file mode 100644 index eff40566d..000000000 --- a/src/cpu/inorder/resources/bpred_unit.cc +++ /dev/null @@ -1,463 +0,0 @@ - -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - */ - -#include <list> -#include <vector> - -#include "arch/utility.hh" -#include "base/trace.hh" -#include "config/the_isa.hh" -#include "cpu/inorder/resources/bpred_unit.hh" -#include "debug/InOrderBPred.hh" -#include "debug/Resource.hh" - -using namespace std; -using namespace ThePipeline; - -BPredUnit::BPredUnit(Resource *_res, ThePipeline::Params *params) - : res(_res), - BTB(params->BTBEntries, params->BTBTagSize, params->instShiftAmt) -{ - // Setup the selected predictor. - if (params->predType == "local") { - localBP = new LocalBP(params->localPredictorSize, - params->localCtrBits, - params->instShiftAmt); - predictor = Local; - } else if (params->predType == "tournament") { - tournamentBP = new TournamentBP(params->localCtrBits, - params->localHistoryTableSize, - params->localHistoryBits, - params->globalPredictorSize, - params->globalHistoryBits, - params->globalCtrBits, - params->choicePredictorSize, - params->choiceCtrBits, - params->instShiftAmt); - predictor = Tournament; - } else { - fatal("Invalid BP selected!"); - } - - for (int i=0; i < ThePipeline::MaxThreads; i++) - RAS[i].init(params->RASSize); - - instSize = sizeof(TheISA::MachInst); -} - -std::string -BPredUnit::name() -{ - return res->name(); -} - -void -BPredUnit::regStats() -{ - lookups - .name(name() + ".lookups") - .desc("Number of BP lookups") - ; - - condPredicted - .name(name() + ".condPredicted") - .desc("Number of conditional branches predicted") - ; - - condIncorrect - .name(name() + ".condIncorrect") - .desc("Number of conditional branches incorrect") - ; - - BTBLookups - .name(name() + ".BTBLookups") - .desc("Number of BTB lookups") - ; - - BTBHits - .name(name() + ".BTBHits") - .desc("Number of BTB hits") - ; - - BTBHitPct - .name(name() + ".BTBHitPct") - .desc("BTB Hit Percentage") - .precision(6); - BTBHitPct = (BTBHits / BTBLookups) * 100; - - usedRAS - .name(name() + ".usedRAS") - .desc("Number of times the RAS was used to get a target.") - ; - - RASIncorrect - .name(name() + ".RASInCorrect") - .desc("Number of incorrect RAS predictions.") - ; -} - - -void -BPredUnit::switchOut() -{ - // Clear any state upon switch out. - for (int i = 0; i < ThePipeline::MaxThreads; ++i) { - squash(0, i); - } -} - - -void -BPredUnit::takeOverFrom() -{ - // Can reset all predictor state, but it's not necessarily better - // than leaving it be. -/* - for (int i = 0; i < ThePipeline::MaxThreads; ++i) - RAS[i].reset(); - - BP.reset(); - BTB.reset(); -*/ -} - - -bool -BPredUnit::predict(DynInstPtr &inst, TheISA::PCState &predPC, ThreadID tid) -{ - // See if branch predictor predicts taken. - // If so, get its target addr either from the BTB or the RAS. - // Save off record of branch stuff so the RAS can be fixed - // up once it's done. - - using TheISA::MachInst; - - int asid = inst->asid; - bool pred_taken = false; - TheISA::PCState target; - - ++lookups; - DPRINTF(InOrderBPred, "[tid:%i] [sn:%i] %s ... PC %s doing branch " - "prediction\n", tid, inst->seqNum, - inst->staticInst->disassemble(inst->instAddr()), - inst->pcState()); - - - void *bp_history = NULL; - - if (inst->isUncondCtrl()) { - DPRINTF(InOrderBPred, "[tid:%i] Unconditional control.\n", - tid); - pred_taken = true; - // Tell the BP there was an unconditional branch. - BPUncond(bp_history); - - if (inst->isReturn() && RAS[tid].empty()) { - DPRINTF(InOrderBPred, "[tid:%i] RAS is empty, predicting " - "false.\n", tid); - pred_taken = false; - } - } else { - ++condPredicted; - - pred_taken = BPLookup(predPC.instAddr(), bp_history); - } - - PredictorHistory predict_record(inst->seqNum, predPC, pred_taken, - bp_history, tid); - - // Now lookup in the BTB or RAS. - if (pred_taken) { - if (inst->isReturn()) { - ++usedRAS; - - // If it's a function return call, then look up the address - // in the RAS. - TheISA::PCState rasTop = RAS[tid].top(); - target = TheISA::buildRetPC(inst->pcState(), rasTop); - - // Record the top entry of the RAS, and its index. - predict_record.usedRAS = true; - predict_record.RASIndex = RAS[tid].topIdx(); - predict_record.rasTarget = rasTop; - - assert(predict_record.RASIndex < 16); - - RAS[tid].pop(); - - DPRINTF(InOrderBPred, "[tid:%i]: Instruction %s is a return, " - "RAS predicted target: %s, RAS index: %i.\n", - tid, inst->pcState(), target, - predict_record.RASIndex); - } else { - ++BTBLookups; - - if (inst->isCall()) { - - RAS[tid].push(inst->pcState()); - - // Record that it was a call so that the top RAS entry can - // be popped off if the speculation is incorrect. - predict_record.wasCall = true; - - DPRINTF(InOrderBPred, "[tid:%i]: Instruction %s was a call" - ", adding %s to the RAS index: %i.\n", - tid, inst->pcState(), predPC, - RAS[tid].topIdx()); - } - - if (inst->isCall() && - inst->isUncondCtrl() && - inst->isDirectCtrl()) { - target = inst->branchTarget(); - } else if (BTB.valid(predPC.instAddr(), asid)) { - ++BTBHits; - - // If it's not a return, use the BTB to get the target addr. - target = BTB.lookup(predPC.instAddr(), asid); - - DPRINTF(InOrderBPred, "[tid:%i]: [asid:%i] Instruction %s " - "predicted target is %s.\n", - tid, asid, inst->pcState(), target); - } else { - DPRINTF(InOrderBPred, "[tid:%i]: BTB doesn't have a " - "valid entry, predicting false.\n",tid); - pred_taken = false; - } - } - } - - if (pred_taken) { - // Set the PC and the instruction's predicted target. - predPC = target; - } - DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Setting Predicted PC to %s.\n", - tid, inst->seqNum, predPC); - - predHist[tid].push_front(predict_record); - - DPRINTF(InOrderBPred, "[tid:%i] [sn:%i] pushed onto front of predHist " - "...predHist.size(): %i\n", - tid, inst->seqNum, predHist[tid].size()); - - return pred_taken; -} - - -void -BPredUnit::update(const InstSeqNum &done_sn, ThreadID tid) -{ - DPRINTF(Resource, "BranchPred: [tid:%i]: Commiting branches until sequence" - "number %lli.\n", tid, done_sn); - - while (!predHist[tid].empty() && - predHist[tid].back().seqNum <= done_sn) { - // Update the branch predictor with the correct results. - BPUpdate(predHist[tid].back().pc.instAddr(), - predHist[tid].back().predTaken, - predHist[tid].back().bpHistory, - false); - - predHist[tid].pop_back(); - } -} - - -void -BPredUnit::squash(const InstSeqNum &squashed_sn, ThreadID tid, ThreadID asid) -{ - History &pred_hist = predHist[tid]; - - while (!pred_hist.empty() && - pred_hist.front().seqNum > squashed_sn) { - if (pred_hist.front().usedRAS) { - DPRINTF(InOrderBPred, "BranchPred: [tid:%i]: Restoring top of RAS " - "to: %i, target: %s.\n", - tid, - pred_hist.front().RASIndex, - pred_hist.front().rasTarget); - - RAS[tid].restore(pred_hist.front().RASIndex, - pred_hist.front().rasTarget); - - } else if (pred_hist.front().wasCall) { - DPRINTF(InOrderBPred, "BranchPred: [tid:%i]: Removing speculative " - "entry added to the RAS.\n",tid); - - RAS[tid].pop(); - } - - // This call should delete the bpHistory. - BPSquash(pred_hist.front().bpHistory); - - pred_hist.pop_front(); - } - -} - - -void -BPredUnit::squash(const InstSeqNum &squashed_sn, - const TheISA::PCState &corrTarget, - bool actually_taken, - ThreadID tid, - ThreadID asid) -{ - // Now that we know that a branch was mispredicted, we need to undo - // all the branches that have been seen up until this branch and - // fix up everything. - - History &pred_hist = predHist[tid]; - - ++condIncorrect; - - DPRINTF(InOrderBPred, "[tid:%i]: Squashing from sequence number %i, " - "setting target to %s.\n", - tid, squashed_sn, corrTarget); - - squash(squashed_sn, tid); - - // If there's a squash due to a syscall, there may not be an entry - // corresponding to the squash. In that case, don't bother trying to - // fix up the entry. - if (!pred_hist.empty()) { - HistoryIt hist_it = pred_hist.begin(); - //HistoryIt hist_it = find(pred_hist.begin(), pred_hist.end(), - // squashed_sn); - - //assert(hist_it != pred_hist.end()); - if (pred_hist.front().seqNum != squashed_sn) { - DPRINTF(InOrderBPred, "Front sn %i != Squash sn %i\n", - pred_hist.front().seqNum, squashed_sn); - - assert(pred_hist.front().seqNum == squashed_sn); - } - - - if ((*hist_it).usedRAS) { - ++RASIncorrect; - } - - BPUpdate((*hist_it).pc.instAddr(), actually_taken, - pred_hist.front().bpHistory, true); - - // only update BTB on branch taken right??? - if (actually_taken) - BTB.update((*hist_it).pc.instAddr(), corrTarget, asid); - - DPRINTF(InOrderBPred, "[tid:%i]: Removing history for [sn:%i] " - "PC %s.\n", tid, (*hist_it).seqNum, (*hist_it).pc); - - pred_hist.erase(hist_it); - - DPRINTF(InOrderBPred, "[tid:%i]: predHist.size(): %i\n", tid, - predHist[tid].size()); - - } else { - DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i] pred_hist empty, can't " - "update.\n", tid, squashed_sn); - } -} - - -void -BPredUnit::BPUncond(void * &bp_history) -{ - // Only the tournament predictor cares about unconditional branches. - if (predictor == Tournament) { - tournamentBP->uncondBr(bp_history); - } -} - - -void -BPredUnit::BPSquash(void *bp_history) -{ - if (predictor == Local) { - localBP->squash(bp_history); - } else if (predictor == Tournament) { - tournamentBP->squash(bp_history); - } else { - panic("Predictor type is unexpected value!"); - } -} - - -bool -BPredUnit::BPLookup(Addr inst_PC, void * &bp_history) -{ - if (predictor == Local) { - return localBP->lookup(inst_PC, bp_history); - } else if (predictor == Tournament) { - return tournamentBP->lookup(inst_PC, bp_history); - } else { - panic("Predictor type is unexpected value!"); - } -} - - -void -BPredUnit::BPUpdate(Addr inst_PC, bool taken, void *bp_history, bool squashed) -{ - if (predictor == Local) { - localBP->update(inst_PC, taken, bp_history); - } else if (predictor == Tournament) { - tournamentBP->update(inst_PC, taken, bp_history, squashed); - } else { - panic("Predictor type is unexpected value!"); - } -} - - -void -BPredUnit::dump() -{ - /*typename History::iterator pred_hist_it; - - for (int i = 0; i < ThePipeline::MaxThreads; ++i) { - if (!predHist[i].empty()) { - pred_hist_it = predHist[i].begin(); - - cprintf("predHist[%i].size(): %i\n", i, predHist[i].size()); - - while (pred_hist_it != predHist[i].end()) { - cprintf("[sn:%lli], PC:%#x, tid:%i, predTaken:%i, " - "bpHistory:%#x\n", - (*pred_hist_it).seqNum, (*pred_hist_it).PC, - (*pred_hist_it).tid, (*pred_hist_it).predTaken, - (*pred_hist_it).bpHistory); - pred_hist_it++; - } - - cprintf("\n"); - } - }*/ -} diff --git a/src/cpu/inorder/resources/bpred_unit.hh b/src/cpu/inorder/resources/bpred_unit.hh deleted file mode 100644 index b5d12d2db..000000000 --- a/src/cpu/inorder/resources/bpred_unit.hh +++ /dev/null @@ -1,267 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - * Korey Sewell - */ - -#ifndef __CPU_INORDER_BPRED_UNIT_HH__ -#define __CPU_INORDER_BPRED_UNIT_HH__ - -#include <list> - -#include "arch/isa_traits.hh" -#include "base/statistics.hh" -#include "cpu/inorder/inorder_dyn_inst.hh" -#include "cpu/inorder/pipeline_traits.hh" -#include "cpu/inorder/resource.hh" -#include "cpu/pred/2bit_local.hh" -#include "cpu/pred/btb.hh" -#include "cpu/pred/ras.hh" -#include "cpu/pred/tournament.hh" -#include "cpu/inst_seq.hh" -#include "params/InOrderCPU.hh" - -/** - * Basically a wrapper class to hold both the branch predictor - * and the BTB. - */ -class BPredUnit -{ - private: - - enum PredType { - Local, - Tournament - }; - - PredType predictor; - - public: - - /** - * @param params The params object, that has the size of the BP and BTB. - */ - BPredUnit(Resource *_res, ThePipeline::Params *params); - - std::string name(); - - /** - * Registers statistics. - */ - void regStats(); - - void switchOut(); - - void takeOverFrom(); - - /** - * Predicts whether or not the instruction is a taken branch, and the - * target of the branch if it is taken. - * @param inst The branch instruction. - * @param predPC The predicted PC is passed back through this parameter. - * @param tid The thread id. - * @return Returns if the branch is taken or not. - */ - bool predict(ThePipeline::DynInstPtr &inst, - TheISA::PCState &predPC, ThreadID tid); - - // @todo: Rename this function. - void BPUncond(void * &bp_history); - - /** - * Tells the branch predictor to commit any updates until the given - * sequence number. - * @param done_sn The sequence number to commit any older updates up until. - * @param tid The thread id. - */ - void update(const InstSeqNum &done_sn, ThreadID tid); - - /** - * Squashes all outstanding updates until a given sequence number. - * @param squashed_sn The sequence number to squash any younger updates up - * until. - * @param tid The thread id. - */ - void squash(const InstSeqNum &squashed_sn, ThreadID tid, - ThreadID asid = 0); - - /** - * Squashes all outstanding updates until a given sequence number, and - * corrects that sn's update with the proper address and taken/not taken. - * @param squashed_sn The sequence number to squash any younger updates up - * until. - * @param corrTarget The correct branch target. - * @param actually_taken The correct branch direction. - * @param tid The thread id. - */ - void squash(const InstSeqNum &squashed_sn, - const TheISA::PCState &corrTarget, bool actually_taken, - ThreadID tid, ThreadID asid = 0); - - /** - * @param bp_history Pointer to the history object. The predictor - * will need to update any state and delete the object. - */ - void BPSquash(void *bp_history); - - /** - * Looks up a given PC in the BP to see if it is taken or not taken. - * @param inst_PC The PC to look up. - * @param bp_history Pointer that will be set to an object that - * has the branch predictor state associated with the lookup. - * @return Whether the branch is taken or not taken. - */ - bool BPLookup(Addr instPC, void * &bp_history); - - /** - * Looks up a given PC in the BTB to see if a matching entry exists. - * @param inst_PC The PC to look up. - * @return Whether the BTB contains the given PC. - */ - bool BTBValid(Addr &inst_PC) - { return BTB.valid(inst_PC, 0); } - - /** - * Looks up a given PC in the BTB to get the predicted target. - * @param inst_PC The PC to look up. - * @return The address of the target of the branch. - */ - TheISA::PCState BTBLookup(Addr instPC) - { return BTB.lookup(instPC, 0); } - - /** - * Updates the BP with taken/not taken information. - * @param instPC The branch's PC that will be updated. - * @param taken Whether the branch was taken or not taken. - * @param bp_history Pointer to the branch predictor state that is - * associated with the branch lookup that is being updated. - * @param squashed if the branch in question was squashed or not - * @todo Make this update flexible enough to handle a global predictor. - */ - void BPUpdate(Addr instPC, bool taken, void *bp_history, bool squashed); - - /** - * Updates the BTB with the target of a branch. - * @param inst_PC The branch's PC that will be updated. - * @param target_PC The branch's target that will be added to the BTB. - */ - void BTBUpdate(Addr instPC, const TheISA::PCState &targetPC) - { BTB.update(instPC, targetPC, 0); } - - void dump(); - - private: - int instSize; - Resource *res; - - struct PredictorHistory { - /** - * Makes a predictor history struct that contains any - * information needed to update the predictor, BTB, and RAS. - */ - PredictorHistory(const InstSeqNum &seq_num, - const TheISA::PCState &instPC, bool pred_taken, - void *bp_history, ThreadID _tid) - : seqNum(seq_num), pc(instPC), rasTarget(0), RASIndex(0), - tid(_tid), predTaken(pred_taken), usedRAS(0), wasCall(0), - bpHistory(bp_history) - {} - - /** The sequence number for the predictor history entry. */ - InstSeqNum seqNum; - - /** The PC associated with the sequence number. */ - TheISA::PCState pc; - - /** The RAS target (only valid if a return). */ - TheISA::PCState rasTarget; - - /** The RAS index of the instruction (only valid if a call). */ - unsigned RASIndex; - - /** The thread id. */ - ThreadID tid; - - /** Whether or not it was predicted taken. */ - bool predTaken; - - /** Whether or not the RAS was used. */ - bool usedRAS; - - /** Whether or not the instruction was a call. */ - bool wasCall; - - /** Pointer to the history object passed back from the branch - * predictor. It is used to update or restore state of the - * branch predictor. - */ - void *bpHistory; - }; - - typedef std::list<PredictorHistory> History; - typedef History::iterator HistoryIt; - - /** - * The per-thread predictor history. This is used to update the predictor - * as instructions are committed, or restore it to the proper state after - * a squash. - */ - History predHist[ThePipeline::MaxThreads]; - - /** The local branch predictor. */ - LocalBP *localBP; - - /** The tournament branch predictor. */ - TournamentBP *tournamentBP; - - /** The BTB. */ - DefaultBTB BTB; - - /** The per-thread return address stack. */ - ReturnAddrStack RAS[ThePipeline::MaxThreads]; - - /** Stat for number of BP lookups. */ - Stats::Scalar lookups; - /** Stat for number of conditional branches predicted. */ - Stats::Scalar condPredicted; - /** Stat for number of conditional branches predicted incorrectly. */ - Stats::Scalar condIncorrect; - /** Stat for number of BTB lookups. */ - Stats::Scalar BTBLookups; - /** Stat for number of BTB hits. */ - Stats::Scalar BTBHits; - /** Stat for number of times the BTB is correct. */ - Stats::Scalar BTBCorrect; - /** Stat for number of times the RAS is used to get a target. */ - Stats::Scalar usedRAS; - /** Stat for number of times the RAS is incorrect. */ - Stats::Scalar RASIncorrect; - Stats::Formula BTBHitPct; -}; - -#endif // __CPU_INORDER_BPRED_UNIT_HH__ diff --git a/src/cpu/inorder/resources/branch_predictor.cc b/src/cpu/inorder/resources/branch_predictor.cc index 004cf8b63..50d3847ba 100644 --- a/src/cpu/inorder/resources/branch_predictor.cc +++ b/src/cpu/inorder/resources/branch_predictor.cc @@ -44,7 +44,7 @@ BranchPredictor::BranchPredictor(std::string res_name, int res_id, InOrderCPU *_cpu, ThePipeline::Params *params) : Resource(res_name, res_id, res_width, res_latency, _cpu), - branchPred(this, params) + branchPred(params->branchPred) { instSize = sizeof(MachInst); } @@ -61,8 +61,6 @@ BranchPredictor::regStats() .desc("Number of Branches Predicted As Not Taken (False)."); Resource::regStats(); - - branchPred.regStats(); } void @@ -97,6 +95,7 @@ BranchPredictor::execute(int slot_num) DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, " "skipping prediction \n", tid, inst->seqNum); } else { + TheISA::PCState instPC = inst->pcState(); TheISA::PCState pred_PC = inst->pcState(); TheISA::advancePC(pred_PC, inst->staticInst); @@ -104,7 +103,9 @@ BranchPredictor::execute(int slot_num) // If not, the pred_PC be updated to pc+8 // If predicted, the pred_PC will be updated to new target // value - bool predict_taken = branchPred.predict(inst, pred_PC, tid); + bool predict_taken = branchPred->predictInOrder( + inst->staticInst, inst->seqNum, + inst->asid, instPC, pred_PC, tid); if (predict_taken) { DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch " @@ -119,8 +120,8 @@ BranchPredictor::execute(int slot_num) inst->setBranchPred(predict_taken); } - //@todo: Check to see how hw_rei is handled here...how does PC,NPC get - // updated to compare mispredict against??? + //@todo: Check to see how hw_rei is handled here...how does + //PC,NPC get updated to compare mispredict against??? inst->setPredTarg(pred_PC); DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: %s Predicted PC is " "%s.\n", tid, seq_num, inst->instName(), pred_PC); @@ -143,7 +144,7 @@ BranchPredictor::execute(int slot_num) tid, seq_num); - branchPred.update(seq_num, tid); + branchPred->update(seq_num, tid); } bpred_req->done(); @@ -165,18 +166,16 @@ BranchPredictor::squash(DynInstPtr inst, int squash_stage, // update due to branch resolution if (squash_stage >= ThePipeline::BackEndStartStage) { - branchPred.squash(bpred_squash_num, - inst->pcState(), - inst->pcState().branching(), - tid); + branchPred->squash(bpred_squash_num, inst->pcState(), + inst->pcState().branching(), tid); } else { // update due to predicted taken branch - branchPred.squash(bpred_squash_num, tid); + branchPred->squash(bpred_squash_num, tid); } } void BranchPredictor::instGraduated(InstSeqNum seq_num, ThreadID tid) { - branchPred.update(seq_num, tid); + branchPred->update(seq_num, tid); } diff --git a/src/cpu/inorder/resources/branch_predictor.hh b/src/cpu/inorder/resources/branch_predictor.hh index dde340ce7..e2b7fba52 100644 --- a/src/cpu/inorder/resources/branch_predictor.hh +++ b/src/cpu/inorder/resources/branch_predictor.hh @@ -36,7 +36,7 @@ #include <string> #include <vector> -#include "cpu/inorder/resources/bpred_unit.hh" +#include "cpu/pred/bpred_unit.hh" #include "cpu/inorder/cpu.hh" #include "cpu/inorder/inorder_dyn_inst.hh" #include "cpu/inorder/pipeline_traits.hh" @@ -70,7 +70,7 @@ class BranchPredictor : public Resource { /** List of instructions this resource is currently * processing. */ - BPredUnit branchPred; + BPredUnit *branchPred; int instSize; |