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-rw-r--r--src/cpu/inorder/resources/agen_unit.cc22
-rw-r--r--src/cpu/inorder/resources/bpred_unit.cc10
-rw-r--r--src/cpu/inorder/resources/bpred_unit.hh14
-rw-r--r--src/cpu/inorder/resources/branch_predictor.cc6
-rw-r--r--src/cpu/inorder/resources/branch_predictor.hh4
-rw-r--r--src/cpu/inorder/resources/cache_unit.cc46
-rw-r--r--src/cpu/inorder/resources/cache_unit.hh2
-rw-r--r--src/cpu/inorder/resources/decode_unit.cc24
-rw-r--r--src/cpu/inorder/resources/decode_unit.hh3
-rw-r--r--src/cpu/inorder/resources/execution_unit.cc4
-rw-r--r--src/cpu/inorder/resources/fetch_seq_unit.cc14
-rw-r--r--src/cpu/inorder/resources/fetch_seq_unit.hh8
-rw-r--r--src/cpu/inorder/resources/graduation_unit.cc20
-rw-r--r--src/cpu/inorder/resources/inst_buffer.cc18
-rw-r--r--src/cpu/inorder/resources/inst_buffer.hh6
-rw-r--r--src/cpu/inorder/resources/inst_buffer_new.cc4
-rw-r--r--src/cpu/inorder/resources/inst_buffer_new.hh2
-rw-r--r--src/cpu/inorder/resources/mult_div_unit.cc4
-rw-r--r--src/cpu/inorder/resources/tlb_unit.cc12
-rw-r--r--src/cpu/inorder/resources/tlb_unit.hh3
-rw-r--r--src/cpu/inorder/resources/use_def.cc7
-rw-r--r--src/cpu/inorder/resources/use_def.hh3
22 files changed, 118 insertions, 118 deletions
diff --git a/src/cpu/inorder/resources/agen_unit.cc b/src/cpu/inorder/resources/agen_unit.cc
index 44cd002ef..44bf8c0ad 100644
--- a/src/cpu/inorder/resources/agen_unit.cc
+++ b/src/cpu/inorder/resources/agen_unit.cc
@@ -42,10 +42,11 @@ AGENUnit::execute(int slot_num)
ResourceRequest* agen_req = reqMap[slot_num];
DynInstPtr inst = reqMap[slot_num]->inst;
Fault fault = reqMap[slot_num]->fault;
- int tid;
+#if TRACING_ON
+ ThreadID tid = inst->readTid();
+#endif
int seq_num = inst->seqNum;
- tid = inst->readTid();
agen_req->fault = NoFault;
switch (agen_req->cmd)
@@ -54,22 +55,27 @@ AGENUnit::execute(int slot_num)
{
// Load/Store Instruction
if (inst->isMemRef()) {
- DPRINTF(InOrderAGEN, "[tid:%i] Generating Address for [sn:%i] (%s).\n",
- tid, inst->seqNum, inst->staticInst->getName());
+ DPRINTF(InOrderAGEN,
+ "[tid:%i] Generating Address for [sn:%i] (%s).\n",
+ tid, seq_num, inst->staticInst->getName());
fault = inst->calcEA();
inst->setMemAddr(inst->getEA());
- DPRINTF(InOrderAGEN, "[tid:%i] [sn:%i] Effective address calculated to be: "
- "%#x.\n", tid, inst->seqNum, inst->getEA());
+ DPRINTF(InOrderAGEN,
+ "[tid:%i] [sn:%i] Effective address calculated as: %#x\n",
+ tid, seq_num, inst->getEA());
if (fault == NoFault) {
agen_req->done();
} else {
- fatal("%s encountered while calculating address for [sn:%i]",fault->name(), seq_num);
+ fatal("%s encountered while calculating address [sn:%i]",
+ fault->name(), seq_num);
}
} else {
- DPRINTF(InOrderAGEN, "[tid:] Ignoring non-memory instruction [sn:%i].\n", tid, seq_num);
+ DPRINTF(InOrderAGEN,
+ "[tid:] Ignoring non-memory instruction [sn:%i]\n",
+ tid, seq_num);
agen_req->done();
}
}
diff --git a/src/cpu/inorder/resources/bpred_unit.cc b/src/cpu/inorder/resources/bpred_unit.cc
index df6b33792..2ed8586aa 100644
--- a/src/cpu/inorder/resources/bpred_unit.cc
+++ b/src/cpu/inorder/resources/bpred_unit.cc
@@ -142,7 +142,7 @@ BPredUnit::takeOverFrom()
bool
-BPredUnit::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
+BPredUnit::predict(DynInstPtr &inst, Addr &PC, ThreadID tid)
{
// See if branch predictor predicts taken.
// If so, get its target addr either from the BTB or the RAS.
@@ -268,7 +268,7 @@ BPredUnit::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
void
-BPredUnit::update(const InstSeqNum &done_sn, unsigned tid)
+BPredUnit::update(const InstSeqNum &done_sn, ThreadID tid)
{
DPRINTF(Resource, "BranchPred: [tid:%i]: Commiting branches until sequence"
"number %lli.\n", tid, done_sn);
@@ -286,7 +286,7 @@ BPredUnit::update(const InstSeqNum &done_sn, unsigned tid)
void
-BPredUnit::squash(const InstSeqNum &squashed_sn, unsigned tid)
+BPredUnit::squash(const InstSeqNum &squashed_sn, ThreadID tid)
{
History &pred_hist = predHist[tid];
@@ -321,8 +321,8 @@ BPredUnit::squash(const InstSeqNum &squashed_sn, unsigned tid)
void
BPredUnit::squash(const InstSeqNum &squashed_sn,
const Addr &corr_target,
- const bool actually_taken,
- unsigned tid)
+ bool actually_taken,
+ ThreadID tid)
{
// Now that we know that a branch was mispredicted, we need to undo
// all the branches that have been seen up until this branch and
diff --git a/src/cpu/inorder/resources/bpred_unit.hh b/src/cpu/inorder/resources/bpred_unit.hh
index bd68459d1..abbb70e0d 100644
--- a/src/cpu/inorder/resources/bpred_unit.hh
+++ b/src/cpu/inorder/resources/bpred_unit.hh
@@ -87,7 +87,7 @@ class BPredUnit
* @param tid The thread id.
* @return Returns if the branch is taken or not.
*/
- bool predict(ThePipeline::DynInstPtr &inst, Addr &PC, unsigned tid);
+ bool predict(ThePipeline::DynInstPtr &inst, Addr &PC, ThreadID tid);
// @todo: Rename this function.
void BPUncond(void * &bp_history);
@@ -98,7 +98,7 @@ class BPredUnit
* @param done_sn The sequence number to commit any older updates up until.
* @param tid The thread id.
*/
- void update(const InstSeqNum &done_sn, unsigned tid);
+ void update(const InstSeqNum &done_sn, ThreadID tid);
/**
* Squashes all outstanding updates until a given sequence number.
@@ -106,7 +106,7 @@ class BPredUnit
* until.
* @param tid The thread id.
*/
- void squash(const InstSeqNum &squashed_sn, unsigned tid);
+ void squash(const InstSeqNum &squashed_sn, ThreadID tid);
/**
* Squashes all outstanding updates until a given sequence number, and
@@ -118,7 +118,7 @@ class BPredUnit
* @param tid The thread id.
*/
void squash(const InstSeqNum &squashed_sn, const Addr &corr_target,
- bool actually_taken, unsigned tid);
+ bool actually_taken, ThreadID tid);
/**
* @param bp_history Pointer to the history object. The predictor
@@ -178,8 +178,8 @@ class BPredUnit
* information needed to update the predictor, BTB, and RAS.
*/
PredictorHistory(const InstSeqNum &seq_num, const Addr &inst_PC,
- const bool pred_taken, void *bp_history,
- const unsigned _tid)
+ bool pred_taken, void *bp_history,
+ ThreadID _tid)
: seqNum(seq_num), PC(inst_PC), RASTarget(0),
RASIndex(0), tid(_tid), predTaken(pred_taken), usedRAS(0),
wasCall(0), bpHistory(bp_history)
@@ -198,7 +198,7 @@ class BPredUnit
unsigned RASIndex;
/** The thread id. */
- unsigned tid;
+ ThreadID tid;
/** Whether or not it was predicted taken. */
bool predTaken;
diff --git a/src/cpu/inorder/resources/branch_predictor.cc b/src/cpu/inorder/resources/branch_predictor.cc
index d8c0730af..905de0794 100644
--- a/src/cpu/inorder/resources/branch_predictor.cc
+++ b/src/cpu/inorder/resources/branch_predictor.cc
@@ -65,7 +65,7 @@ BranchPredictor::execute(int slot_num)
ResourceRequest* bpred_req = reqMap[slot_num];
DynInstPtr inst = bpred_req->inst;
- int tid = inst->readTid();
+ ThreadID tid = inst->readTid();
int seq_num = inst->seqNum;
//int stage_num = bpred_req->getStageNum();
@@ -136,14 +136,14 @@ BranchPredictor::execute(int slot_num)
void
BranchPredictor::squash(DynInstPtr inst, int squash_stage,
- InstSeqNum squash_seq_num, unsigned tid)
+ InstSeqNum squash_seq_num, ThreadID tid)
{
DPRINTF(InOrderBPred, "Squashing...\n");
branchPred.squash(squash_seq_num, tid);
}
void
-BranchPredictor::instGraduated(InstSeqNum seq_num,unsigned tid)
+BranchPredictor::instGraduated(InstSeqNum seq_num, ThreadID tid)
{
branchPred.update(seq_num, tid);
}
diff --git a/src/cpu/inorder/resources/branch_predictor.hh b/src/cpu/inorder/resources/branch_predictor.hh
index 47053910d..7d0b3348a 100644
--- a/src/cpu/inorder/resources/branch_predictor.hh
+++ b/src/cpu/inorder/resources/branch_predictor.hh
@@ -61,9 +61,9 @@ class BranchPredictor : public Resource {
virtual void execute(int slot_num);
virtual void squash(DynInstPtr inst, int stage_num,
- InstSeqNum squash_seq_num, unsigned tid);
+ InstSeqNum squash_seq_num, ThreadID tid);
- virtual void instGraduated(InstSeqNum seq_num,unsigned tid);
+ virtual void instGraduated(InstSeqNum seq_num, ThreadID tid);
protected:
/** List of instructions this resource is currently
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 5d5d4d45d..5677810f6 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -258,17 +258,10 @@ Fault
CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
int flags, TheISA::TLB::Mode tlb_mode)
{
- int tid;
- int seq_num;
- Addr aligned_addr;
- unsigned stage_num;
- unsigned slot_idx;
-
- tid = inst->readTid();
- seq_num = inst->seqNum;
- aligned_addr = inst->getMemAddr();
- stage_num = cache_req->getStageNum();
- slot_idx = cache_req->getSlot();
+ ThreadID tid = inst->readTid();
+ Addr aligned_addr = inst->getMemAddr();
+ unsigned stage_num = cache_req->getStageNum();
+ unsigned slot_idx = cache_req->getSlot();
if (tlb_mode == TheISA::TLB::Execute) {
inst->fetchMemReq = new Request(inst->readTid(), aligned_addr,
@@ -290,7 +283,7 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
if (cache_req->fault != NoFault) {
DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "
"addr:%08p for [sn:%i].\n", tid, cache_req->fault->name(),
- cache_req->memReq->getVaddr(), seq_num);
+ cache_req->memReq->getVaddr(), inst->seqNum);
cpu->pipelineStage[stage_num]->setResStall(cache_req, tid);
@@ -303,7 +296,7 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
cpu->trap(cache_req->fault, tid);
} else {
DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated "
- "to phys. addr:%08p.\n", tid, seq_num,
+ "to phys. addr:%08p.\n", tid, inst->seqNum,
cache_req->memReq->getVaddr(),
cache_req->memReq->getPaddr());
}
@@ -361,11 +354,11 @@ CacheUnit::execute(int slot_num)
assert(cache_req);
DynInstPtr inst = cache_req->inst;
- int tid;
- int seq_num;
+#if TRACING_ON
+ ThreadID tid = inst->readTid();
+ int seq_num = inst->seqNum;
+#endif
- tid = inst->readTid();
- seq_num = inst->seqNum;
cache_req->fault = NoFault;
switch (cache_req->cmd)
@@ -381,8 +374,8 @@ CacheUnit::execute(int slot_num)
if (cache_req->fault == NoFault) {
DPRINTF(InOrderCachePort,
- "[tid:%u]: Initiating fetch access to %s for addr. %08p\n",
- tid, name(), cache_req->inst->getMemAddr());
+ "[tid:%u]: Initiating fetch access to %s for addr. %08p\n",
+ tid, name(), cache_req->inst->getMemAddr());
cache_req->reqData = new uint8_t[acc_size];
@@ -499,9 +492,9 @@ Fault
CacheUnit::doCacheAccess(DynInstPtr inst, uint64_t *write_res)
{
Fault fault = NoFault;
- int tid = 0;
-
- tid = inst->readTid();
+#if TRACING_ON
+ ThreadID tid = inst->readTid();
+#endif
CacheReqPtr cache_req
= dynamic_cast<CacheReqPtr>(reqMap[inst->getCurResSlot()]);
@@ -627,10 +620,7 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
// Get resource request info
unsigned stage_num = cache_req->getStageNum();
DynInstPtr inst = cache_req->inst;
- unsigned tid;
-
-
- tid = cache_req->inst->readTid();
+ ThreadID tid = cache_req->inst->readTid();
if (!cache_req->isSquashed()) {
if (inst->resSched.top()->cmd == CompleteFetch) {
@@ -752,7 +742,7 @@ CacheUnitEvent::process()
{
DynInstPtr inst = resource->reqMap[slotIdx]->inst;
int stage_num = resource->reqMap[slotIdx]->getStageNum();
- int tid = inst->threadNumber;
+ ThreadID tid = inst->threadNumber;
CacheReqPtr req_ptr = dynamic_cast<CacheReqPtr>(resource->reqMap[slotIdx]);
DPRINTF(InOrderTLB, "Waking up from TLB Miss caused by [sn:%i].\n",
@@ -774,7 +764,7 @@ CacheUnitEvent::process()
void
CacheUnit::squash(DynInstPtr inst, int stage_num,
- InstSeqNum squash_seq_num, unsigned tid)
+ InstSeqNum squash_seq_num, ThreadID tid)
{
vector<int> slot_remove_list;
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index aba5a1b0c..8946ad5d3 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -144,7 +144,7 @@ class CacheUnit : public Resource
void execute(int slot_num);
void squash(DynInstPtr inst, int stage_num,
- InstSeqNum squash_seq_num, unsigned tid);
+ InstSeqNum squash_seq_num, ThreadID tid);
/** Processes cache completion event. */
void processCacheCompletion(PacketPtr pkt);
diff --git a/src/cpu/inorder/resources/decode_unit.cc b/src/cpu/inorder/resources/decode_unit.cc
index d95b1d4bb..033c318f2 100644
--- a/src/cpu/inorder/resources/decode_unit.cc
+++ b/src/cpu/inorder/resources/decode_unit.cc
@@ -39,7 +39,7 @@ DecodeUnit::DecodeUnit(std::string res_name, int res_id, int res_width,
int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
: Resource(res_name, res_id, res_width, res_latency, _cpu)
{
- for (int tid = 0; tid < MaxThreads; tid++) {
+ for (ThreadID tid = 0; tid < MaxThreads; tid++) {
regDepMap[tid] = &cpu->archRegDepMap[tid];
}
}
@@ -50,10 +50,8 @@ DecodeUnit::execute(int slot_num)
ResourceRequest* decode_req = reqMap[slot_num];
DynInstPtr inst = reqMap[slot_num]->inst;
Fault fault = reqMap[slot_num]->fault;
- int tid, seq_num;
+ ThreadID tid = inst->readTid();
- tid = inst->readTid();
- seq_num = inst->seqNum;
decode_req->fault = NoFault;
switch (decode_req->cmd)
@@ -63,13 +61,17 @@ DecodeUnit::execute(int slot_num)
bool done_sked = ThePipeline::createBackEndSchedule(inst);
if (done_sked) {
- DPRINTF(InOrderDecode, "[tid:%i]: Setting Destination Register(s) for [sn:%i].\n",
- tid, seq_num);
+ DPRINTF(InOrderDecode,
+ "[tid:%i]: Setting Destination Register(s) for [sn:%i].\n",
+ tid, inst->seqNum);
regDepMap[tid]->insert(inst);
decode_req->done();
} else {
- DPRINTF(Resource,"[tid:%i] Static Inst not available to decode. Unable to create "
- "schedule for instruction [sn:%i] \n", tid, inst->seqNum);
+ DPRINTF(Resource,
+ "[tid:%i] Static Inst not available to decode.\n", tid);
+ DPRINTF(Resource,
+ "Unable to create schedule for instruction [sn:%i] \n",
+ inst->seqNum);
DPRINTF(InOrderStall, "STALL: \n");
decode_req->done(false);
}
@@ -83,9 +85,11 @@ DecodeUnit::execute(int slot_num)
void
-DecodeUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid)
+DecodeUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
+ ThreadID tid)
{
- DPRINTF(InOrderDecode, "[tid:%i]: Updating due to squash from stage %i after [sn:%i].\n",
+ DPRINTF(InOrderDecode,
+ "[tid:%i]: Updating due to squash from stage %i after [sn:%i].\n",
tid, stage_num, squash_seq_num);
//cpu->removeInstsUntil(squash_seq_num, tid);
diff --git a/src/cpu/inorder/resources/decode_unit.hh b/src/cpu/inorder/resources/decode_unit.hh
index 3813de6c4..1a700c211 100644
--- a/src/cpu/inorder/resources/decode_unit.hh
+++ b/src/cpu/inorder/resources/decode_unit.hh
@@ -57,7 +57,8 @@ class DecodeUnit : public Resource {
virtual void execute(int slot_num);
- void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid);
+ void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
+ ThreadID tid);
RegDepMap *regDepMap[ThePipeline::MaxThreads];
diff --git a/src/cpu/inorder/resources/execution_unit.cc b/src/cpu/inorder/resources/execution_unit.cc
index 16f00b1be..c9072b5d5 100644
--- a/src/cpu/inorder/resources/execution_unit.cc
+++ b/src/cpu/inorder/resources/execution_unit.cc
@@ -63,7 +63,7 @@ ExecutionUnit::execute(int slot_num)
ResourceRequest* exec_req = reqMap[slot_num];
DynInstPtr inst = reqMap[slot_num]->inst;
Fault fault = reqMap[slot_num]->fault;
- int tid = inst->readTid();
+ ThreadID tid = inst->readTid();
int seq_num = inst->seqNum;
exec_req->fault = NoFault;
@@ -89,7 +89,7 @@ ExecutionUnit::execute(int slot_num)
// that got squashed.
if (inst->mispredicted()) {
int stage_num = exec_req->getStageNum();
- int tid = inst->readTid();
+ ThreadID tid = inst->readTid();
// If it's a branch ...
if (inst->isDirectCtrl()) {
diff --git a/src/cpu/inorder/resources/fetch_seq_unit.cc b/src/cpu/inorder/resources/fetch_seq_unit.cc
index 69610ae58..bc809b040 100644
--- a/src/cpu/inorder/resources/fetch_seq_unit.cc
+++ b/src/cpu/inorder/resources/fetch_seq_unit.cc
@@ -41,7 +41,7 @@ FetchSeqUnit::FetchSeqUnit(std::string res_name, int res_id, int res_width,
: Resource(res_name, res_id, res_width, res_latency, _cpu),
instSize(sizeof(MachInst))
{
- for (int tid = 0; tid < ThePipeline::MaxThreads; tid++) {
+ for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
delaySlotInfo[tid].numInsts = 0;
delaySlotInfo[tid].targetReady = false;
@@ -68,7 +68,7 @@ FetchSeqUnit::execute(int slot_num)
// for performance considerations
ResourceRequest* fs_req = reqMap[slot_num];
DynInstPtr inst = fs_req->inst;
- int tid = inst->readTid();
+ ThreadID tid = inst->readTid();
int stage_num = fs_req->getStageNum();
int seq_num = inst->seqNum;
@@ -202,7 +202,7 @@ FetchSeqUnit::execute(int slot_num)
}
inline void
-FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, unsigned tid)
+FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid)
{
// Squash In Pipeline Stage
cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid);
@@ -216,7 +216,7 @@ FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, unsigned tid)
}
void
FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
- InstSeqNum squash_seq_num, unsigned tid)
+ InstSeqNum squash_seq_num, ThreadID tid)
{
DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating due to squash from stage %i.\n",
tid, squash_stage);
@@ -302,7 +302,7 @@ FetchSeqUnit::FetchSeqEvent::process()
void
-FetchSeqUnit::activateThread(unsigned tid)
+FetchSeqUnit::activateThread(ThreadID tid)
{
pcValid[tid] = true;
@@ -317,7 +317,7 @@ FetchSeqUnit::activateThread(unsigned tid)
}
void
-FetchSeqUnit::deactivateThread(unsigned tid)
+FetchSeqUnit::deactivateThread(ThreadID tid)
{
delaySlotInfo[tid].numInsts = 0;
delaySlotInfo[tid].targetReady = false;
@@ -328,7 +328,7 @@ FetchSeqUnit::deactivateThread(unsigned tid)
squashSeqNum[tid] = (InstSeqNum)-1;
lastSquashCycle[tid] = 0;
- std::list<unsigned>::iterator thread_it = find(cpu->fetchPriorityList.begin(),
+ list<ThreadID>::iterator thread_it = find(cpu->fetchPriorityList.begin(),
cpu->fetchPriorityList.end(),
tid);
diff --git a/src/cpu/inorder/resources/fetch_seq_unit.hh b/src/cpu/inorder/resources/fetch_seq_unit.hh
index 1885d1f11..3e18d47cb 100644
--- a/src/cpu/inorder/resources/fetch_seq_unit.hh
+++ b/src/cpu/inorder/resources/fetch_seq_unit.hh
@@ -56,8 +56,8 @@ class FetchSeqUnit : public Resource {
virtual ~FetchSeqUnit() {}
virtual void init();
- virtual void activateThread(unsigned tid);
- virtual void deactivateThread(unsigned tid);
+ virtual void activateThread(ThreadID tid);
+ virtual void deactivateThread(ThreadID tid);
virtual void execute(int slot_num);
/** Override default Resource squash sequence. This actually,
@@ -65,10 +65,10 @@ class FetchSeqUnit : public Resource {
* info
*/
virtual void squash(DynInstPtr inst, int squash_stage,
- InstSeqNum squash_seq_num, unsigned tid);
+ InstSeqNum squash_seq_num, ThreadID tid);
- inline void squashAfterInst(DynInstPtr inst, int stage_num, unsigned tid);
+ inline void squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid);
protected:
unsigned instSize;
diff --git a/src/cpu/inorder/resources/graduation_unit.cc b/src/cpu/inorder/resources/graduation_unit.cc
index 569401e4f..2d7cd5c8c 100644
--- a/src/cpu/inorder/resources/graduation_unit.cc
+++ b/src/cpu/inorder/resources/graduation_unit.cc
@@ -39,7 +39,7 @@ GraduationUnit::GraduationUnit(std::string res_name, int res_id, int res_width,
lastCycleGrad(0), numCycleGrad(0)
{
- for (int tid = 0; tid < ThePipeline::MaxThreads; tid++) {
+ for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
nonSpecInstActive[tid] = &cpu->nonSpecInstActive[tid];
nonSpecSeqNum[tid] = &cpu->nonSpecSeqNum[tid];
}
@@ -51,10 +51,7 @@ GraduationUnit::execute(int slot_num)
ResourceRequest* grad_req = reqMap[slot_num];
DynInstPtr inst = reqMap[slot_num]->inst;
Fault fault = reqMap[slot_num]->fault;
- int tid, seq_num;
-
- tid = inst->readTid();
- seq_num = inst->seqNum;
+ ThreadID tid = inst->readTid();
int stage_num = inst->resSched.top()->stageNum;
grad_req->fault = NoFault;
@@ -70,15 +67,17 @@ GraduationUnit::execute(int slot_num)
lastCycleGrad = curTick;
numCycleGrad = 0;
} else if (numCycleGrad > width) {
- DPRINTF(InOrderGraduation, "Graduation bandwidth reached for this cycle.\n");
+ DPRINTF(InOrderGraduation,
+ "Graduation bandwidth reached for this cycle.\n");
return;
}
// Make sure this is the last thing on the resource schedule
assert(inst->resSched.size() == 1);
- DPRINTF(InOrderGraduation, "[tid:%i] Graduating instruction [sn:%i].\n",
- tid, seq_num);
+ DPRINTF(InOrderGraduation,
+ "[tid:%i] Graduating instruction [sn:%i].\n",
+ tid, inst->seqNum);
DPRINTF(RefCount, "Refcount = %i.\n", 0/*inst->curCount()*/);
@@ -87,8 +86,9 @@ GraduationUnit::execute(int slot_num)
// @TODO: Fix this functionality. Probably too conservative.
if (inst->isNonSpeculative()) {
*nonSpecInstActive[tid] = false;
- DPRINTF(InOrderGraduation, "[tid:%i] Non-speculative instruction [sn:%i] has graduated.\n",
- tid, seq_num);
+ DPRINTF(InOrderGraduation,
+ "[tid:%i] Non-speculative inst [sn:%i] graduated\n",
+ tid, inst->seqNum);
}
if (inst->traceData) {
diff --git a/src/cpu/inorder/resources/inst_buffer.cc b/src/cpu/inorder/resources/inst_buffer.cc
index fafff1fa7..21df1d053 100644
--- a/src/cpu/inorder/resources/inst_buffer.cc
+++ b/src/cpu/inorder/resources/inst_buffer.cc
@@ -60,11 +60,9 @@ InstBuffer::execute(int slot_idx)
{
ResReqPtr ib_req = reqMap[slot_idx];
DynInstPtr inst = ib_req->inst;
- int tid, seq_num, stage_num;
+ ThreadID tid = inst->readTid();
+ int stage_num = ib_req->getStageNum();
- tid = inst->readTid();
- seq_num = inst->seqNum;
- stage_num = ib_req->getStageNum();
ib_req->fault = NoFault;
switch (ib_req->cmd)
@@ -121,12 +119,12 @@ InstBuffer::execute(int slot_idx)
if (instList.size() < width) {
DPRINTF(InOrderInstBuffer, "[tid:%i]: Inserting [sn:%i] into buffer.\n",
- tid, seq_num);
+ tid, inst->seqNum);
insert(inst);
inserted = true;
} else {
DPRINTF(InOrderInstBuffer, "[tid:%i]: Denying [sn:%i] request because "
- "buffer is full.\n", tid, seq_num);
+ "buffer is full.\n", tid, inst->seqNum);
std::list<DynInstPtr>::iterator list_it = instList.begin();
@@ -145,7 +143,7 @@ InstBuffer::execute(int slot_idx)
case RemoveInst:
{
DPRINTF(InOrderInstBuffer, "[tid:%i]: Removing [sn:%i] from buffer.\n",
- tid, seq_num);
+ tid, inst->seqNum);
remove(inst);
ib_req->done();
}
@@ -180,20 +178,20 @@ InstBuffer::remove(DynInstPtr inst)
}
void
-InstBuffer::pop(unsigned tid)
+InstBuffer::pop(ThreadID tid)
{
instList.pop_front();
}
ThePipeline::DynInstPtr
-InstBuffer::top(unsigned tid)
+InstBuffer::top(ThreadID tid)
{
return instList.front();
}
void
InstBuffer::squash(DynInstPtr inst, int stage_num,
- InstSeqNum squash_seq_num, unsigned tid)
+ InstSeqNum squash_seq_num, ThreadID tid)
{
queue<list<DynInstPtr>::iterator> remove_list;
list<DynInstPtr>::iterator list_it = instList.begin();
diff --git a/src/cpu/inorder/resources/inst_buffer.hh b/src/cpu/inorder/resources/inst_buffer.hh
index baadd42ff..7342df66f 100644
--- a/src/cpu/inorder/resources/inst_buffer.hh
+++ b/src/cpu/inorder/resources/inst_buffer.hh
@@ -67,12 +67,12 @@ class InstBuffer : public Resource {
virtual void remove(DynInstPtr inst);
- virtual void pop(unsigned tid);
+ virtual void pop(ThreadID tid);
- virtual DynInstPtr top(unsigned tid);
+ virtual DynInstPtr top(ThreadID tid);
virtual void squash(DynInstPtr inst, int stage_num,
- InstSeqNum squash_seq_num, unsigned tid);
+ InstSeqNum squash_seq_num, ThreadID tid);
protected:
/** List of instructions this resource is currently
* processing.
diff --git a/src/cpu/inorder/resources/inst_buffer_new.cc b/src/cpu/inorder/resources/inst_buffer_new.cc
index 7e2c98837..cc534ef3e 100644
--- a/src/cpu/inorder/resources/inst_buffer_new.cc
+++ b/src/cpu/inorder/resources/inst_buffer_new.cc
@@ -67,7 +67,7 @@ InstBuffer::execute(int slot_idx)
assert(ib_req);
DynInstPtr inst = ib_req->inst;
- int tid = inst->readTid();
+ ThreadID tid = inst->readTid();
int seq_num = inst->seqNum;
ib_req->fault = NoFault;
@@ -128,7 +128,7 @@ InstBuffer::top()
{ return instList.front(); }
void
-InstBuffer::squash(InstSeqNum squash_seq_num, unsigned tid)
+InstBuffer::squash(InstSeqNum squash_seq_num, ThreadID tid)
{
list<DynInstPtr>::iterator list_it = instList.begin();
list<DynInstPtr>::iterator list_end = instList.end();
diff --git a/src/cpu/inorder/resources/inst_buffer_new.hh b/src/cpu/inorder/resources/inst_buffer_new.hh
index e374fa109..b1d5a7b09 100644
--- a/src/cpu/inorder/resources/inst_buffer_new.hh
+++ b/src/cpu/inorder/resources/inst_buffer_new.hh
@@ -71,7 +71,7 @@ class InstBuffer : public Resource {
virtual DynInstPtr top();
- virtual void squash(InstSeqNum squash_seq_num, unsigned tid);
+ virtual void squash(InstSeqNum squash_seq_num, ThreadID tid);
protected:
/** List of instructions this resource is currently
diff --git a/src/cpu/inorder/resources/mult_div_unit.cc b/src/cpu/inorder/resources/mult_div_unit.cc
index df9d4c293..7592c0260 100644
--- a/src/cpu/inorder/resources/mult_div_unit.cc
+++ b/src/cpu/inorder/resources/mult_div_unit.cc
@@ -174,7 +174,7 @@ MultDivUnit::execute(int slot_num)
DynInstPtr inst = reqMap[slot_num]->inst;
Fault fault = reqMap[slot_num]->fault;
- //int tid = inst->readTid();
+ //ThreadID tid = inst->readTid();
//int seq_num = inst->seqNum;
switch (mult_div_req->cmd)
@@ -248,7 +248,7 @@ MultDivUnit::exeMulDiv(int slot_num)
ResourceRequest* mult_div_req = reqMap[slot_num];
DynInstPtr inst = reqMap[slot_num]->inst;
Fault fault = reqMap[slot_num]->fault;
- int tid = inst->readTid();
+ ThreadID tid = inst->readTid();
int seq_num = inst->seqNum;
fault = inst->execute();
diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc
index 1ce8ff8c2..95bade36a 100644
--- a/src/cpu/inorder/resources/tlb_unit.cc
+++ b/src/cpu/inorder/resources/tlb_unit.cc
@@ -101,11 +101,9 @@ TLBUnit::execute(int slot_idx)
assert(tlb_req != 0x0);
DynInstPtr inst = tlb_req->inst;
- int tid, seq_num, stage_num;
-
- tid = inst->readTid();
- seq_num = inst->seqNum;
- stage_num = tlb_req->getStageNum();
+ ThreadID tid = inst->readTid();
+ int seq_num = inst->seqNum;
+ int stage_num = tlb_req->getStageNum();
tlb_req->fault = NoFault;
@@ -202,7 +200,7 @@ TLBUnitEvent::process()
{
DynInstPtr inst = resource->reqMap[slotIdx]->inst;
int stage_num = resource->reqMap[slotIdx]->getStageNum();
- int tid = inst->threadNumber;
+ ThreadID tid = inst->threadNumber;
DPRINTF(InOrderTLB, "Waking up from TLB Miss caused by [sn:%i].\n",
inst->seqNum);
@@ -224,7 +222,7 @@ TLBUnitEvent::process()
void
TLBUnit::squash(DynInstPtr inst, int stage_num,
- InstSeqNum squash_seq_num, unsigned tid)
+ InstSeqNum squash_seq_num, ThreadID tid)
{
//@TODO: Figure out a way to consolidate common parts
// of this squash code
diff --git a/src/cpu/inorder/resources/tlb_unit.hh b/src/cpu/inorder/resources/tlb_unit.hh
index 8f0291b48..1c08bd822 100644
--- a/src/cpu/inorder/resources/tlb_unit.hh
+++ b/src/cpu/inorder/resources/tlb_unit.hh
@@ -67,7 +67,8 @@ class TLBUnit : public Resource
virtual void execute(int slot_num);
- void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid);
+ void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
+ ThreadID tid);
bool tlbBlocked[ThePipeline::MaxThreads];
diff --git a/src/cpu/inorder/resources/use_def.cc b/src/cpu/inorder/resources/use_def.cc
index 53145640e..b30a3a1bf 100644
--- a/src/cpu/inorder/resources/use_def.cc
+++ b/src/cpu/inorder/resources/use_def.cc
@@ -45,7 +45,7 @@ UseDefUnit::UseDefUnit(string res_name, int res_id, int res_width,
: Resource(res_name, res_id, res_width, res_latency, _cpu),
maxSeqNum((InstSeqNum)-1)
{
- for (int tid = 0; tid < ThePipeline::MaxThreads; tid++) {
+ for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
nonSpecInstActive[tid] = &cpu->nonSpecInstActive[tid];
nonSpecSeqNum[tid] = &cpu->nonSpecSeqNum[tid];
@@ -99,7 +99,7 @@ UseDefUnit::execute(int slot_idx)
assert(ud_req);
DynInstPtr inst = ud_req->inst;
- int tid = inst->readTid();
+ ThreadID tid = inst->readTid();
int seq_num = inst->seqNum;
int ud_idx = ud_req->useDefIdx;
@@ -306,7 +306,8 @@ UseDefUnit::execute(int slot_idx)
}
void
-UseDefUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid)
+UseDefUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
+ ThreadID tid)
{
DPRINTF(InOrderUseDef, "[tid:%i]: Updating Due To Squash After [sn:%i].\n",
tid, squash_seq_num);
diff --git a/src/cpu/inorder/resources/use_def.hh b/src/cpu/inorder/resources/use_def.hh
index 51ec2c3f2..6c76d8ab5 100644
--- a/src/cpu/inorder/resources/use_def.hh
+++ b/src/cpu/inorder/resources/use_def.hh
@@ -65,7 +65,8 @@ class UseDefUnit : public Resource {
virtual void execute(int slot_num);
- virtual void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid);
+ virtual void squash(DynInstPtr inst, int stage_num,
+ InstSeqNum squash_seq_num, ThreadID tid);
const InstSeqNum maxSeqNum;