diff options
Diffstat (limited to 'src/cpu/inorder/resources')
-rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 52 | ||||
-rw-r--r-- | src/cpu/inorder/resources/use_def.cc | 6 |
2 files changed, 21 insertions, 37 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 620ba06c1..c38e5541d 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -488,49 +488,33 @@ CacheUnit::read(DynInstPtr inst, Addr addr, if (secondAddr > addr && !inst->split2ndAccess) { - DPRINTF(InOrderCachePort, "%i: sn[%i] Split Read Access (1 of 2) for " - "(%#x, %#x).\n", curTick(), inst->seqNum, addr, secondAddr); - - // Save All "Total" Split Information - // ============================== - inst->splitInst = true; - inst->splitMemData = new uint8_t[size]; - - if (!inst->splitInstSked) { - assert(0 && "Split Requests Not Supported for Now..."); - // Schedule Split Read/Complete for Instruction - // ============================== - int stage_num = cache_req->getStageNum(); - RSkedPtr inst_sked = (stage_num >= ThePipeline::BackEndStartStage) ? - inst->backSked : inst->frontSked; + if (!inst->splitInst) { + DPRINTF(InOrderCachePort, "%i: sn[%i] Split Read Access (1 of 2) for " + "(%#x, %#x).\n", curTick(), inst->seqNum, addr, secondAddr); - // this is just an arbitrarily high priority to ensure that this - // gets pushed to the back of the list - int stage_pri = 20; - - int isplit_cmd = CacheUnit::InitSecondSplitRead; - inst_sked->push(new - ScheduleEntry(stage_num, - stage_pri, - cpu->resPool->getResIdx(DCache), - isplit_cmd, - 1)); + unsigned stage_num = cache_req->getStageNum(); + unsigned cmd = inst->curSkedEntry->cmd; - int csplit_cmd = CacheUnit::CompleteSecondSplitRead; - inst_sked->push(new - ScheduleEntry(stage_num + 1, - 1/*stage_pri*/, - cpu->resPool->getResIdx(DCache), - csplit_cmd, - 1)); - inst->splitInstSked = true; + // 1. Make A New Inst. Schedule w/Split Read/Complete Entered on + // the schedule + // ============================== + // 2. Reassign curSkedPtr to current command (InitiateRead) on new + // schedule + // ============================== + inst->splitInst = true; + inst->setBackSked(cpu->createBackEndSked(inst)); + inst->curSkedEntry = inst->backSked->find(stage_num, cmd); } else { DPRINTF(InOrderCachePort, "[tid:%i] [sn:%i] Retrying Split Read " "Access (1 of 2) for (%#x, %#x).\n", inst->readTid(), inst->seqNum, addr, secondAddr); } + // Save All "Total" Split Information + // ============================== + inst->splitMemData = new uint8_t[size]; + // Split Information for First Access // ============================== size = secondAddr - addr; diff --git a/src/cpu/inorder/resources/use_def.cc b/src/cpu/inorder/resources/use_def.cc index d8bf8790b..642998021 100644 --- a/src/cpu/inorder/resources/use_def.cc +++ b/src/cpu/inorder/resources/use_def.cc @@ -198,7 +198,7 @@ UseDefUnit::execute(int slot_idx) uniqueIntRegMap[flat_idx] = true; DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading Int Reg %i" - " (%i) from Register File:%i.\n", + " (%i) from Register File:0x%x.\n", tid, seq_num, reg_idx, flat_idx, cpu->readIntReg(flat_idx,inst->readTid())); @@ -232,7 +232,7 @@ UseDefUnit::execute(int slot_idx) { uniqueMiscRegMap[flat_idx] = true; DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading Misc Reg %i " - " (%i) from Register File:%i.\n", + " (%i) from Register File:0x%x.\n", tid, seq_num, reg_idx - Ctrl_Base_DepTag, flat_idx, cpu->readMiscReg(flat_idx, @@ -265,7 +265,7 @@ UseDefUnit::execute(int slot_idx) { DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest." " reg %i (%i), value 0x%x from " - "[sn:%i] to [sn:%i] source #%i.\n", + "[sn:%i] to [sn:%i] source #%x.\n", tid, reg_idx, flat_idx, forward_inst->readIntResult(dest_reg_idx), forward_inst->seqNum, |