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-rw-r--r--src/cpu/inorder/InOrderCPU.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py
index 920b9cdc1..dddcbbcec 100644
--- a/src/cpu/inorder/InOrderCPU.py
+++ b/src/cpu/inorder/InOrderCPU.py
@@ -29,7 +29,7 @@
from m5.params import *
from m5.proxy import *
from BaseCPU import BaseCPU
-from BranchPredictor import BranchPredictor
+from BranchPredictor import *
class ThreadModel(Enum):
vals = ['Single', 'SMT', 'SwitchOnCacheMiss']
@@ -72,6 +72,6 @@ class InOrderCPU(BaseCPU):
div32Latency = Param.Cycles(1, "Latency for 32-bit Divide Operations")
div32RepeatRate = Param.Cycles(1, "Repeat Rate for 32-bit Divide Operations")
- branchPred = Param.BranchPredictor(BranchPredictor(numThreads =
+ branchPred = Param.BranchPredictor(TournamentBP(numThreads =
Parent.numThreads),
"Branch Predictor")