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-rw-r--r--src/cpu/inorder/cpu.cc14
-rw-r--r--src/cpu/inorder/cpu.hh15
-rw-r--r--src/cpu/inorder/inorder_dyn_inst.cc2
-rw-r--r--src/cpu/inorder/inorder_dyn_inst.hh2
-rw-r--r--src/cpu/inorder/resource.hh2
-rw-r--r--src/cpu/inorder/resource_pool.cc2
-rw-r--r--src/cpu/inorder/resource_pool.hh2
-rw-r--r--src/cpu/inorder/resources/cache_unit.cc2
-rw-r--r--src/cpu/inorder/resources/cache_unit.hh2
-rw-r--r--src/cpu/inorder/resources/fetch_seq_unit.cc2
-rw-r--r--src/cpu/inorder/resources/fetch_seq_unit.hh2
-rw-r--r--src/cpu/inorder/resources/fetch_unit.cc2
-rw-r--r--src/cpu/inorder/resources/fetch_unit.hh2
13 files changed, 26 insertions, 25 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index e966e8e83..c825f2979 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -128,8 +128,8 @@ InOrderCPU::TickEvent::description() const
}
InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
- Fault fault, ThreadID _tid, DynInstPtr inst,
- CPUEventPri event_pri)
+ const Fault &fault, ThreadID _tid,
+ DynInstPtr inst, CPUEventPri event_pri)
: Event(event_pri), cpu(_cpu)
{
setEvent(e_type, fault, _tid, inst);
@@ -910,7 +910,7 @@ InOrderCPU::getInterrupts()
}
void
-InOrderCPU::processInterrupts(Fault interrupt)
+InOrderCPU::processInterrupts(const Fault &interrupt)
{
// Check for interrupts here. For now can copy the code that
// exists within isa_fullsys_traits.hh. Also assume that thread 0
@@ -928,7 +928,7 @@ InOrderCPU::processInterrupts(Fault interrupt)
}
void
-InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
+InOrderCPU::trapContext(const Fault &fault, ThreadID tid, DynInstPtr inst,
Cycles delay)
{
scheduleCpuEvent(Trap, fault, tid, inst, delay);
@@ -936,7 +936,7 @@ InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
}
void
-InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+InOrderCPU::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
{
fault->invoke(tcBase(tid), inst->staticInst);
removePipelineStalls(tid);
@@ -970,7 +970,7 @@ InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
}
void
-InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
+InOrderCPU::scheduleCpuEvent(CPUEventType c_event, const Fault &fault,
ThreadID tid, DynInstPtr inst,
Cycles delay, CPUEventPri event_pri)
{
@@ -1847,7 +1847,7 @@ InOrderCPU::wakeup()
}
void
-InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
+InOrderCPU::syscallContext(const Fault &fault, ThreadID tid, DynInstPtr inst,
Cycles delay)
{
// Syscall must be non-speculative, so squash from last stage
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 0104cb95f..7efd5ae21 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -263,11 +263,11 @@ class InOrderCPU : public BaseCPU
public:
/** Constructs a CPU event. */
- CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
+ CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, const Fault &fault,
ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
/** Set Type of Event To Be Scheduled */
- void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
+ void setEvent(CPUEventType e_type, const Fault &_fault, ThreadID _tid,
DynInstPtr _inst)
{
fault = _fault;
@@ -291,7 +291,8 @@ class InOrderCPU : public BaseCPU
};
/** Schedule a CPU Event */
- void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
+ void scheduleCpuEvent(CPUEventType cpu_event, const Fault &fault,
+ ThreadID tid,
DynInstPtr inst, Cycles delay = Cycles(0),
CPUEventPri event_pri = InOrderCPU_Pri);
@@ -471,7 +472,7 @@ class InOrderCPU : public BaseCPU
Fault getInterrupts();
/** Processes any an interrupt fault. */
- void processInterrupts(Fault interrupt);
+ void processInterrupts(const Fault &interrupt);
/** Halts the CPU. */
void halt() { panic("Halt not implemented!\n"); }
@@ -483,18 +484,18 @@ class InOrderCPU : public BaseCPU
bool validDataAddr(Addr addr) { return true; }
/** Schedule a syscall on the CPU */
- void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
+ void syscallContext(const Fault &fault, ThreadID tid, DynInstPtr inst,
Cycles delay = Cycles(0));
/** Executes a syscall.*/
void syscall(int64_t callnum, ThreadID tid);
/** Schedule a trap on the CPU */
- void trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
+ void trapContext(const Fault &fault, ThreadID tid, DynInstPtr inst,
Cycles delay = Cycles(0));
/** Perform trap to Handle Given Fault */
- void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+ void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
/** Schedule thread activation on the CPU */
void activateContext(ThreadID tid, Cycles delay = Cycles(0));
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index d0d308f7a..08f583338 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -298,7 +298,7 @@ InOrderDynInst::hwrei()
void
-InOrderDynInst::trap(Fault fault)
+InOrderDynInst::trap(const Fault &fault)
{
this->cpu->trap(fault, this->threadNumber, this);
}
diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index 759da4b04..7558df7d1 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -524,7 +524,7 @@ class InOrderDynInst : public ExecContext, public RefCounted
/** Calls hardware return from error interrupt. */
Fault hwrei();
/** Traps to handle specified fault. */
- void trap(Fault fault);
+ void trap(const Fault &fault);
bool simPalCheck(int palFunc);
short syscallNum;
diff --git a/src/cpu/inorder/resource.hh b/src/cpu/inorder/resource.hh
index ef712d5c9..eaecc2824 100644
--- a/src/cpu/inorder/resource.hh
+++ b/src/cpu/inorder/resource.hh
@@ -104,7 +104,7 @@ class Resource {
virtual void instGraduated(InstSeqNum seq_num, ThreadID tid) { }
/** Post-processsing for Trap Generated from this instruction */
- virtual void trap(Fault fault, ThreadID tid, DynInstPtr inst) { }
+ virtual void trap(const Fault &fault, ThreadID tid, DynInstPtr inst) { }
/** Request usage of this resource. Returns a ResourceRequest object
* with all the necessary resource information
diff --git a/src/cpu/inorder/resource_pool.cc b/src/cpu/inorder/resource_pool.cc
index c09f6c31d..e0f23235e 100644
--- a/src/cpu/inorder/resource_pool.cc
+++ b/src/cpu/inorder/resource_pool.cc
@@ -206,7 +206,7 @@ ResourcePool::squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num,
}
void
-ResourcePool::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+ResourcePool::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
{
DPRINTF(Resource, "[tid:%i] Broadcasting Trap to all "
"resources.\n", tid);
diff --git a/src/cpu/inorder/resource_pool.hh b/src/cpu/inorder/resource_pool.hh
index 2720ed10a..9e3198e1e 100644
--- a/src/cpu/inorder/resource_pool.hh
+++ b/src/cpu/inorder/resource_pool.hh
@@ -193,7 +193,7 @@ class ResourcePool {
void instGraduated(InstSeqNum seq_num, ThreadID tid);
/** Broadcast trap to all resources */
- void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+ void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
/** The number of instructions available that a resource can
* can still process.
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index dea4f91fb..251369e01 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -405,7 +405,7 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
}
void
-CacheUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+CacheUnit::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
{
tlbBlocked[tid] = false;
}
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index 9a7faf9cd..65f18eedb 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -113,7 +113,7 @@ class CacheUnit : public Resource
bool processSquash(CacheReqPacket *cache_pkt);
- void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+ void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
void recvRetry();
diff --git a/src/cpu/inorder/resources/fetch_seq_unit.cc b/src/cpu/inorder/resources/fetch_seq_unit.cc
index 03741b55c..ead4953fb 100644
--- a/src/cpu/inorder/resources/fetch_seq_unit.cc
+++ b/src/cpu/inorder/resources/fetch_seq_unit.cc
@@ -304,7 +304,7 @@ FetchSeqUnit::suspendThread(ThreadID tid)
}
void
-FetchSeqUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+FetchSeqUnit::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
{
pcValid[tid] = true;
pc[tid] = cpu->pcState(tid);
diff --git a/src/cpu/inorder/resources/fetch_seq_unit.hh b/src/cpu/inorder/resources/fetch_seq_unit.hh
index 4cb18a1c7..a8db85b06 100644
--- a/src/cpu/inorder/resources/fetch_seq_unit.hh
+++ b/src/cpu/inorder/resources/fetch_seq_unit.hh
@@ -71,7 +71,7 @@ class FetchSeqUnit : public Resource {
InstSeqNum squash_seq_num, ThreadID tid);
/** Update to correct PC from a trap */
- void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+ void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
protected:
unsigned instSize;
diff --git a/src/cpu/inorder/resources/fetch_unit.cc b/src/cpu/inorder/resources/fetch_unit.cc
index 49bd0434b..6892688b2 100644
--- a/src/cpu/inorder/resources/fetch_unit.cc
+++ b/src/cpu/inorder/resources/fetch_unit.cc
@@ -574,7 +574,7 @@ FetchUnit::squashCacheRequest(CacheReqPtr req_ptr)
}
void
-FetchUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+FetchUnit::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
{
//@todo: per thread?
decoder[tid]->reset();
diff --git a/src/cpu/inorder/resources/fetch_unit.hh b/src/cpu/inorder/resources/fetch_unit.hh
index d1c7b22c0..d72721009 100644
--- a/src/cpu/inorder/resources/fetch_unit.hh
+++ b/src/cpu/inorder/resources/fetch_unit.hh
@@ -87,7 +87,7 @@ class FetchUnit : public CacheUnit
/** Executes one of the commands from the "Command" enum */
void execute(int slot_num);
- void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+ void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
TheISA::Decoder *decoder[ThePipeline::MaxThreads];
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 12:38:07 +0000