diff options
Diffstat (limited to 'src/cpu/inorder')
-rw-r--r-- | src/cpu/inorder/InOrderCPU.py | 20 | ||||
-rw-r--r-- | src/cpu/inorder/params.hh | 20 |
2 files changed, 20 insertions, 20 deletions
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py index 416b18dd3..119de7f1c 100644 --- a/src/cpu/inorder/InOrderCPU.py +++ b/src/cpu/inorder/InOrderCPU.py @@ -65,13 +65,13 @@ class InOrderCPU(BaseCPU): stageTracing = Param.Bool(False, "Enable tracing of each stage in CPU") - multLatency = Param.Unsigned(1, "Latency for Multiply Operations") - multRepeatRate = Param.Unsigned(1, "Repeat Rate for Multiply Operations") - div8Latency = Param.Unsigned(1, "Latency for 8-bit Divide Operations") - div8RepeatRate = Param.Unsigned(1, "Repeat Rate for 8-bit Divide Operations") - div16Latency = Param.Unsigned(1, "Latency for 16-bit Divide Operations") - div16RepeatRate = Param.Unsigned(1, "Repeat Rate for 16-bit Divide Operations") - div24Latency = Param.Unsigned(1, "Latency for 24-bit Divide Operations") - div24RepeatRate = Param.Unsigned(1, "Repeat Rate for 24-bit Divide Operations") - div32Latency = Param.Unsigned(1, "Latency for 32-bit Divide Operations") - div32RepeatRate = Param.Unsigned(1, "Repeat Rate for 32-bit Divide Operations") + multLatency = Param.Cycles(1, "Latency for Multiply Operations") + multRepeatRate = Param.Cycles(1, "Repeat Rate for Multiply Operations") + div8Latency = Param.Cycles(1, "Latency for 8-bit Divide Operations") + div8RepeatRate = Param.Cycles(1, "Repeat Rate for 8-bit Divide Operations") + div16Latency = Param.Cycles(1, "Latency for 16-bit Divide Operations") + div16RepeatRate = Param.Cycles(1, "Repeat Rate for 16-bit Divide Operations") + div24Latency = Param.Cycles(1, "Latency for 24-bit Divide Operations") + div24RepeatRate = Param.Cycles(1, "Repeat Rate for 24-bit Divide Operations") + div32Latency = Param.Cycles(1, "Latency for 32-bit Divide Operations") + div32RepeatRate = Param.Cycles(1, "Repeat Rate for 32-bit Divide Operations") diff --git a/src/cpu/inorder/params.hh b/src/cpu/inorder/params.hh index 44f2a5018..a4ffdf70b 100644 --- a/src/cpu/inorder/params.hh +++ b/src/cpu/inorder/params.hh @@ -97,24 +97,24 @@ class InOrderParams : public BaseCPU::Params // then MDU must be defined as its own SimObject so that an arbitrary # can // be defined with different parameters /** Latency & Repeat Rate for Multiply Insts */ - unsigned multLatency; - unsigned multRepeatRate; + Cycles multLatency; + Cycles multRepeatRate; /** Latency & Repeat Rate for 8-bit Divide Insts */ - unsigned div8Latency; - unsigned div8RepeatRate; + Cycles div8Latency; + Cycles div8RepeatRate; /** Latency & Repeat Rate for 16-bit Divide Insts */ - unsigned div16Latency; - unsigned div16RepeatRate; + Cycles div16Latency; + Cycles div16RepeatRate; /** Latency & Repeat Rate for 24-bit Divide Insts */ - unsigned div24Latency; - unsigned div24RepeatRate; + Cycles div24Latency; + Cycles div24RepeatRate; /** Latency & Repeat Rate for 32-bit Divide Insts */ - unsigned div32Latency; - unsigned div32RepeatRate; + Cycles div32Latency; + Cycles div32RepeatRate; }; |