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-rw-r--r--src/cpu/inorder/cpu.cc6
-rw-r--r--src/cpu/inorder/first_stage.cc7
-rw-r--r--src/cpu/inorder/inorder_dyn_inst.cc6
-rw-r--r--src/cpu/inorder/pipeline_stage.cc21
-rw-r--r--src/cpu/inorder/pipeline_stage.hh2
-rw-r--r--src/cpu/inorder/resources/cache_unit.cc7
-rw-r--r--src/cpu/inorder/resources/fetch_seq_unit.cc5
-rw-r--r--src/cpu/inorder/resources/graduation_unit.cc7
-rw-r--r--src/cpu/inorder/resources/mult_div_unit.cc27
-rw-r--r--src/cpu/inorder/resources/mult_div_unit.hh10
-rw-r--r--src/cpu/inorder/thread_context.hh1
11 files changed, 33 insertions, 66 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 7dafd826f..70877aae4 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -147,6 +147,8 @@ InOrderCPU::CPUEvent::unscheduleEvent()
InOrderCPU::InOrderCPU(Params *params)
: BaseCPU(params),
cpu_id(params->cpu_id),
+ coreType("default"),
+ _status(Idle),
tickEvent(this),
miscRegFile(this),
timeBuffer(2 , 2),
@@ -162,10 +164,6 @@ InOrderCPU::InOrderCPU(Params *params)
resPool = new ResourcePool(this, params);
- coreType = "default"; // eventually get this from params
-
- _status = Idle;
-
// Resize for Multithreading CPUs
thread.resize(numThreads);
diff --git a/src/cpu/inorder/first_stage.cc b/src/cpu/inorder/first_stage.cc
index be4431a03..5e389b256 100644
--- a/src/cpu/inorder/first_stage.cc
+++ b/src/cpu/inorder/first_stage.cc
@@ -40,15 +40,12 @@ using namespace std;
using namespace ThePipeline;
FirstStage::FirstStage(Params *params, unsigned stage_num)
- : PipelineStage(params, stage_num)
+ : PipelineStage(params, stage_num), numFetchingThreads(1),
+ fetchPolicy(FirstStage::RoundRobin)
{
for(int tid=0; tid < this->numThreads; tid++) {
stageStatus[tid] = Running;
}
-
- numFetchingThreads = 1;
-
- fetchPolicy = RoundRobin;
}
void
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index d292d72f0..ceb3cbe51 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -76,16 +76,14 @@ InOrderDynInst::InOrderDynInst(InOrderCPU *cpu,
}
InOrderDynInst::InOrderDynInst(StaticInstPtr &_staticInst)
- : staticInst(_staticInst), traceData(NULL)
+ : seqNum(0), staticInst(_staticInst), traceData(NULL)
{
- seqNum = 0;
initVars();
}
InOrderDynInst::InOrderDynInst()
- : traceData(NULL), cpu(cpu)
+ : seqNum(0), traceData(NULL), cpu(cpu)
{
- seqNum = 0;
initVars();
}
diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc
index ab7328f4a..cb69464b0 100644
--- a/src/cpu/inorder/pipeline_stage.cc
+++ b/src/cpu/inorder/pipeline_stage.cc
@@ -38,24 +38,17 @@ using namespace std;
using namespace ThePipeline;
PipelineStage::PipelineStage(Params *params, unsigned stage_num)
+ : stageNum(stage_num), stageWidth(ThePipeline::StageWidth),
+ numThreads(ThePipeline::MaxThreads), _status(Inactive),
+ stageBufferMax(ThePipeline::interStageBuffSize[stage_num]),
+ prevStageValid(false), nextStageValid(false)
{
- init(params, stage_num);
+ init(params);
}
void
-PipelineStage::init(Params *params, unsigned stage_num)
+PipelineStage::init(Params *params)
{
- stageNum = stage_num;
- stageWidth = ThePipeline::StageWidth;
-
- _status = Inactive;
-
- numThreads = ThePipeline::MaxThreads;
-
- prevStageValid = false;
- nextStageValid = false;
-
- // Init. structures
for(int tid=0; tid < numThreads; tid++) {
stageStatus[tid] = Idle;
@@ -69,8 +62,6 @@ PipelineStage::init(Params *params, unsigned stage_num)
else
lastStallingStage[tid] = NumStages - 1;
}
-
- stageBufferMax = ThePipeline::interStageBuffSize[stage_num];
}
diff --git a/src/cpu/inorder/pipeline_stage.hh b/src/cpu/inorder/pipeline_stage.hh
index 19bf8154f..2fd8f2215 100644
--- a/src/cpu/inorder/pipeline_stage.hh
+++ b/src/cpu/inorder/pipeline_stage.hh
@@ -97,7 +97,7 @@ class PipelineStage
virtual ~PipelineStage() { }
/** PipelineStage initialization. */
- void init(Params *params, unsigned stage_num);
+ void init(Params *params);
/** Returns the name of stage. */
std::string name() const;
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 6fd7ae36c..57bcb10ef 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -81,14 +81,9 @@ CacheUnit::CachePort::recvRetry()
CacheUnit::CacheUnit(string res_name, int res_id, int res_width,
int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
: Resource(res_name, res_id, res_width, res_latency, _cpu),
- retryPkt(NULL), retrySlot(-1)
+ retryPkt(NULL), retrySlot(-1), cacheBlocked(false)
{
- //cacheData.resize(res_width);
- //slotStatus = new CachePortStatus[width];
- //fetchPC = new Addr[width];
cachePort = new CachePort(this);
-
- cacheBlocked = false;
}
Port *
diff --git a/src/cpu/inorder/resources/fetch_seq_unit.cc b/src/cpu/inorder/resources/fetch_seq_unit.cc
index 36cf714c9..444252e1b 100644
--- a/src/cpu/inorder/resources/fetch_seq_unit.cc
+++ b/src/cpu/inorder/resources/fetch_seq_unit.cc
@@ -38,10 +38,9 @@ using namespace ThePipeline;
FetchSeqUnit::FetchSeqUnit(std::string res_name, int res_id, int res_width,
int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
- : Resource(res_name, res_id, res_width, res_latency, _cpu)
+ : Resource(res_name, res_id, res_width, res_latency, _cpu),
+ instSize(sizeof(MachInst))
{
- instSize = sizeof(MachInst);
-
for (int tid = 0; tid < ThePipeline::MaxThreads; tid++) {
delaySlotInfo[tid].numInsts = 0;
delaySlotInfo[tid].targetReady = false;
diff --git a/src/cpu/inorder/resources/graduation_unit.cc b/src/cpu/inorder/resources/graduation_unit.cc
index 701da5996..569401e4f 100644
--- a/src/cpu/inorder/resources/graduation_unit.cc
+++ b/src/cpu/inorder/resources/graduation_unit.cc
@@ -35,11 +35,10 @@ using namespace ThePipeline;
GraduationUnit::GraduationUnit(std::string res_name, int res_id, int res_width,
int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
- : Resource(res_name, res_id, res_width, res_latency, _cpu)
+ : Resource(res_name, res_id, res_width, res_latency, _cpu),
+ lastCycleGrad(0), numCycleGrad(0)
+
{
- lastCycleGrad = 0;
- numCycleGrad = 0;
-
for (int tid = 0; tid < ThePipeline::MaxThreads; tid++) {
nonSpecInstActive[tid] = &cpu->nonSpecInstActive[tid];
nonSpecSeqNum[tid] = &cpu->nonSpecSeqNum[tid];
diff --git a/src/cpu/inorder/resources/mult_div_unit.cc b/src/cpu/inorder/resources/mult_div_unit.cc
index e98e97be7..b31d60ad5 100644
--- a/src/cpu/inorder/resources/mult_div_unit.cc
+++ b/src/cpu/inorder/resources/mult_div_unit.cc
@@ -41,25 +41,14 @@ using namespace ThePipeline;
MultDivUnit::MultDivUnit(string res_name, int res_id, int res_width,
int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
- : Resource(res_name, res_id, res_width, res_latency, _cpu)
-{
- multRepeatRate = params->multRepeatRate;
- multLatency = params->multLatency;
-
- div8RepeatRate = params->div8RepeatRate;
- div8Latency = params->div8Latency;
-
- div16RepeatRate = params->div16RepeatRate;
- div16Latency = params->div16Latency;
-
- div24RepeatRate = params->div24RepeatRate;
- div24Latency = params->div24Latency;
-
- div32RepeatRate = params->div32RepeatRate;
- div32Latency = params->div32Latency;
-
- lastMDUCycle = 0;
-}
+ : Resource(res_name, res_id, res_width, res_latency, _cpu),
+ multRepeatRate(params->multRepeatRate), multLatency(params->multLatency),
+ div8RepeatRate(params->div8RepeatRate), div8Latency(params->div8Latency),
+ div16RepeatRate(params->div16RepeatRate), div16Latency(params->div16Latency),
+ div24RepeatRate(params->div24RepeatRate), div24Latency(params->div24Latency),
+ div32RepeatRate(params->div32RepeatRate), div32Latency(params->div32Latency),
+ lastMDUCycle(0)
+{ }
void
MultDivUnit::regStats()
diff --git a/src/cpu/inorder/resources/mult_div_unit.hh b/src/cpu/inorder/resources/mult_div_unit.hh
index 762442c4b..003f6fbb1 100644
--- a/src/cpu/inorder/resources/mult_div_unit.hh
+++ b/src/cpu/inorder/resources/mult_div_unit.hh
@@ -84,24 +84,24 @@ class MultDivUnit : public Resource {
protected:
/** Latency & Repeat Rate for Multiply Insts */
- unsigned multLatency;
unsigned multRepeatRate;
+ unsigned multLatency;
/** Latency & Repeat Rate for 8-bit Divide Insts */
- unsigned div8Latency;
unsigned div8RepeatRate;
+ unsigned div8Latency;
/** Latency & Repeat Rate for 16-bit Divide Insts */
- unsigned div16Latency;
unsigned div16RepeatRate;
+ unsigned div16Latency;
/** Latency & Repeat Rate for 24-bit Divide Insts */
- unsigned div24Latency;
unsigned div24RepeatRate;
+ unsigned div24Latency;
/** Latency & Repeat Rate for 32-bit Divide Insts */
- unsigned div32Latency;
unsigned div32RepeatRate;
+ unsigned div32Latency;
/** Last cycle that MDU was used */
Tick lastMDUCycle;
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 8b3b47290..2fb2ed85f 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -132,6 +132,7 @@ class InOrderThreadContext : public ThreadContext
/** Serializes state. */
virtual void serialize(std::ostream &os);
+
/** Unserializes state. */
virtual void unserialize(Checkpoint *cp, const std::string &section);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 11:40:14 +0000