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-rw-r--r--src/cpu/inorder/cpu.cc4
-rw-r--r--src/cpu/inorder/cpu.hh4
-rw-r--r--src/cpu/inorder/resources/cache_unit.cc2
3 files changed, 4 insertions, 6 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 04176c54f..7e75dfbb8 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -88,10 +88,8 @@ InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit) :
{ }
bool
-InOrderCPU::CachePort::recvTiming(Packet *pkt)
+InOrderCPU::CachePort::recvTimingResp(Packet *pkt)
{
- assert(pkt->isResponse());
-
if (pkt->isError())
DPRINTF(InOrderCachePort, "Got error packet back for address: %x\n",
pkt->getAddr());
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 06d733d85..bb52c6023 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -170,13 +170,13 @@ class InOrderCPU : public BaseCPU
protected:
/** Timing version of receive */
- bool recvTiming(PacketPtr pkt);
+ bool recvTimingResp(PacketPtr pkt);
/** Handles doing a retry of a failed timing request. */
void recvRetry();
/** Ignoring snoops for now. */
- bool recvTimingSnoop(PacketPtr pkt) { return true; }
+ void recvTimingSnoopReq(PacketPtr pkt) { }
};
/** Define TickEvent for the CPU */
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index a5bb9cd24..a4dc23d47 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -873,7 +873,7 @@ CacheUnit::doCacheAccess(DynInstPtr inst, uint64_t *write_res,
tid, inst->seqNum, cache_req->dataPkt->getAddr());
if (do_access) {
- if (!cachePort->sendTiming(cache_req->dataPkt)) {
+ if (!cachePort->sendTimingReq(cache_req->dataPkt)) {
DPRINTF(InOrderCachePort,
"[tid:%i] [sn:%i] cannot access cache, because port "
"is blocked. now waiting to retry request\n", tid,