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-rw-r--r--src/cpu/inorder/InOrderCPU.py3
-rw-r--r--src/cpu/inorder/cpu.cc14
-rw-r--r--src/cpu/inorder/cpu.hh4
-rw-r--r--src/cpu/inorder/resources/cache_unit.cc23
-rw-r--r--src/cpu/inorder/resources/cache_unit.hh15
-rw-r--r--src/cpu/inorder/thread_context.cc6
-rw-r--r--src/cpu/inorder/thread_context.hh15
7 files changed, 17 insertions, 63 deletions
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py
index 4766a1ac1..40af48b19 100644
--- a/src/cpu/inorder/InOrderCPU.py
+++ b/src/cpu/inorder/InOrderCPU.py
@@ -44,9 +44,6 @@ class InOrderCPU(BaseCPU):
fetchMemPort = Param.String("icache_port" , "Name of Memory Port to get instructions from")
dataMemPort = Param.String("dcache_port" , "Name of Memory Port to get data from")
- icache_port = Port("Instruction Port")
- dcache_port = Port("Data Port")
- _cached_ports = ['icache_port', 'dcache_port']
fetchBuffSize = Param.Unsigned(4, "Fetch Buffer Size (Number of Cache Blocks Stored)")
memBlockSize = Param.Unsigned(64, "Memory Block Size")
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 010bdb512..5a14e92a7 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -54,7 +54,6 @@
#include "debug/RefCount.hh"
#include "debug/SkedCache.hh"
#include "debug/Quiesce.hh"
-#include "mem/translating_port.hh"
#include "params/InOrderCPU.hh"
#include "sim/full_system.hh"
#include "sim/process.hh"
@@ -758,6 +757,8 @@ InOrderCPU::init()
for (ThreadID tid = 0; tid < numThreads; tid++) {
ThreadContext *src_tc = threadContexts[tid];
TheISA::initCPU(src_tc, src_tc->contextId());
+ // Initialise the ThreadContext's memory proxies
+ thread[tid]->initMemProxies(thread[tid]->getTC());
}
}
@@ -860,7 +861,6 @@ InOrderCPU::getInterrupts()
return interrupts->getInterrupt(threadContexts[0]);
}
-
void
InOrderCPU::processInterrupts(Fault interrupt)
{
@@ -880,16 +880,6 @@ InOrderCPU::processInterrupts(Fault interrupt)
}
void
-InOrderCPU::updateMemPorts()
-{
- // Update all ThreadContext's memory ports (Functional/Virtual
- // Ports)
- ThreadID size = thread.size();
- for (ThreadID i = 0; i < size; ++i)
- thread[i]->connectMemPorts(thread[i]->getTC());
-}
-
-void
InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
{
scheduleCpuEvent(Trap, fault, tid, inst, delay);
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index bbd02e027..7d22bc902 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -428,10 +428,6 @@ class InOrderCPU : public BaseCPU
/** Halts the CPU. */
void halt() { panic("Halt not implemented!\n"); }
- /** Update the Virt and Phys ports of all ThreadContexts to
- * reflect change in memory connections. */
- void updateMemPorts();
-
/** Check if this address is a valid instruction address. */
bool validInstAddr(Addr addr) { return true; }
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 90ed83d68..0ab9f0579 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -82,17 +82,8 @@ CacheUnit::CachePort::recvFunctional(PacketPtr pkt)
}
void
-CacheUnit::CachePort::recvStatusChange(Status status)
+CacheUnit::CachePort::recvRangeChange()
{
- if (status == RangeChange) {
- if (!snoopRangeSent) {
- snoopRangeSent = true;
- sendStatusChange(Port::RangeChange);
- }
- return;
- }
-
- panic("CacheUnit::CachePort doesn't expect recvStatusChange callback!");
}
bool
@@ -145,18 +136,6 @@ CacheUnit::tlb()
}
-void
-CacheUnit::CachePort::setPeer(Port *port)
-{
- Port::setPeer(port);
-
- // Update the ThreadContext's memory ports (Functional/Virtual
- // Ports)
- if (cachePortUnit->resName == "dcache_port") {
- cachePortUnit->cpu->updateMemPorts();
- }
-}
-
Port *
CacheUnit::getPort(const string &if_name, int idx)
{
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index a8dde512b..2155c920c 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -90,13 +90,9 @@ class CacheUnit : public Resource
CachePort(CacheUnit *_cachePortUnit)
: Port(_cachePortUnit->name() + "-cache-port",
(MemObject*)_cachePortUnit->cpu),
- cachePortUnit(_cachePortUnit), snoopRangeSent(false)
+ cachePortUnit(_cachePortUnit)
{ }
- bool snoopRangeSent;
-
- void setPeer(Port *port);
-
protected:
/** Atomic version of receive. Panics. */
Tick recvAtomic(PacketPtr pkt);
@@ -104,13 +100,8 @@ class CacheUnit : public Resource
/** Functional version of receive.*/
void recvFunctional(PacketPtr pkt);
- /** Receives status change. Other than range changing, panics. */
- void recvStatusChange(Status status);
-
- /** Returns the address ranges of this device. */
- void getDeviceAddressRanges(AddrRangeList &resp,
- bool &snoop)
- { resp.clear(); snoop = true; }
+ /** Receives range changes. */
+ void recvRangeChange();
/** Timing version of receive */
bool recvTiming(PacketPtr pkt);
diff --git a/src/cpu/inorder/thread_context.cc b/src/cpu/inorder/thread_context.cc
index 5f141a1b3..acfcf0939 100644
--- a/src/cpu/inorder/thread_context.cc
+++ b/src/cpu/inorder/thread_context.cc
@@ -38,10 +38,10 @@
using namespace TheISA;
-VirtualPort *
-InOrderThreadContext::getVirtPort()
+FSTranslatingPortProxy*
+InOrderThreadContext::getVirtProxy()
{
- return thread->getVirtPort();
+ return thread->getVirtProxy();
}
void
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 84d62137e..7fe0fb5ef 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -117,8 +117,12 @@ class InOrderThreadContext : public ThreadContext
TheISA::Kernel::Statistics *getKernelStats()
{ return thread->kernelStats; }
- void connectMemPorts(ThreadContext *tc)
- { thread->connectMemPorts(tc); }
+ PortProxy* getPhysProxy() { return thread->getPhysProxy(); }
+
+ FSTranslatingPortProxy* getVirtProxy();
+
+ void initMemProxies(ThreadContext *tc)
+ { thread->initMemProxies(tc); }
/** Dumps the function profiling information.
* @todo: Implement.
@@ -142,14 +146,11 @@ class InOrderThreadContext : public ThreadContext
return this->thread->quiesceEvent;
}
+ SETranslatingPortProxy* getMemProxy() { return thread->getMemProxy(); }
+
/** Returns a pointer to this thread's process. */
Process *getProcessPtr() { return thread->getProcessPtr(); }
- TranslatingPort *getMemPort() { return thread->getMemPort(); }
-
- VirtualPort *getVirtPort();
- FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
-
/** Returns this thread's status. */
Status status() const { return thread->status(); }
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 12:53:55 +0000