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-rw-r--r--src/cpu/inorder/cpu.cc15
-rw-r--r--src/cpu/inorder/cpu.hh10
-rw-r--r--src/cpu/inorder/inorder_dyn_inst.cc4
-rw-r--r--src/cpu/inorder/resource.hh7
-rw-r--r--src/cpu/inorder/resources/agen_unit.cc35
-rw-r--r--src/cpu/inorder/resources/cache_unit.cc58
-rw-r--r--src/cpu/inorder/resources/cache_unit.hh4
-rw-r--r--src/cpu/inorder/resources/tlb_unit.cc4
-rw-r--r--src/cpu/inorder/resources/tlb_unit.hh4
9 files changed, 105 insertions, 36 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index c5f06c3b2..e17d82041 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -1264,6 +1264,21 @@ InOrderCPU::write(DynInstPtr inst)
return mem_res->doDataAccess(inst);
}
+void
+InOrderCPU::prefetch(DynInstPtr inst)
+{
+ Resource *mem_res = resPool->getResource(dataPortIdx);
+ return mem_res->prefetch(inst);
+}
+
+void
+InOrderCPU::writeHint(DynInstPtr inst)
+{
+ Resource *mem_res = resPool->getResource(dataPortIdx);
+ return mem_res->writeHint(inst);
+}
+
+
TheISA::TLB*
InOrderCPU::getITBPtr()
{
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index fda2e4366..9426171c1 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -497,6 +497,16 @@ class InOrderCPU : public BaseCPU
*/
Fault write(DynInstPtr inst);
+ /** Forwards an instruction prefetch to the appropriate data
+ * resource (indexes into Resource Pool thru "dataPortIdx")
+ */
+ void prefetch(DynInstPtr inst);
+
+ /** Forwards an instruction writeHint to the appropriate data
+ * resource (indexes into Resource Pool thru "dataPortIdx")
+ */
+ void writeHint(DynInstPtr inst);
+
/** Executes a syscall.*/
void syscall(int64_t callnum, int tid);
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index 692e3ff73..9355a9f6f 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -296,13 +296,13 @@ InOrderDynInst::syscall(int64_t callnum)
void
InOrderDynInst::prefetch(Addr addr, unsigned flags)
{
- panic("Prefetch Unimplemented\n");
+ cpu->prefetch(this);
}
void
InOrderDynInst::writeHint(Addr addr, int size, unsigned flags)
{
- panic("Write-Hint Unimplemented\n");
+ cpu->writeHint(this);
}
/**
diff --git a/src/cpu/inorder/resource.hh b/src/cpu/inorder/resource.hh
index b857e59ed..0c0aad758 100644
--- a/src/cpu/inorder/resource.hh
+++ b/src/cpu/inorder/resource.hh
@@ -143,6 +143,13 @@ class Resource {
virtual Fault doDataAccess(DynInstPtr inst)
{ panic("doDataAccess undefined for %s", name()); return NoFault; }
+ virtual void prefetch(DynInstPtr inst)
+ { panic("prefetch undefined for %s", name()); }
+
+ virtual void writeHint(DynInstPtr inst)
+ { panic("doDataAccess undefined for %s", name()); }
+
+
/** Squash All Requests After This Seq Num */
virtual void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid);
diff --git a/src/cpu/inorder/resources/agen_unit.cc b/src/cpu/inorder/resources/agen_unit.cc
index f462b12ea..44cd002ef 100644
--- a/src/cpu/inorder/resources/agen_unit.cc
+++ b/src/cpu/inorder/resources/agen_unit.cc
@@ -55,35 +55,18 @@ AGENUnit::execute(int slot_num)
// Load/Store Instruction
if (inst->isMemRef()) {
DPRINTF(InOrderAGEN, "[tid:%i] Generating Address for [sn:%i] (%s).\n",
- tid, inst->seqNum, inst->staticInst->getName());
+ tid, inst->seqNum, inst->staticInst->getName());
+ fault = inst->calcEA();
+ inst->setMemAddr(inst->getEA());
- // We are not handdling Prefetches quite yet
- if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
- panic("Prefetches arent handled yet.\n");
- } else {
- if (inst->isLoad()) {
- fault = inst->calcEA();
- inst->setMemAddr(inst->getEA());
- //inst->setExecuted();
-
- DPRINTF(InOrderAGEN, "[tid:%i] [sn:%i] Effective address calculated to be: "
- "%#x.\n", tid, inst->seqNum, inst->getEA());
- } else if (inst->isStore()) {
- fault = inst->calcEA();
- inst->setMemAddr(inst->getEA());
+ DPRINTF(InOrderAGEN, "[tid:%i] [sn:%i] Effective address calculated to be: "
+ "%#x.\n", tid, inst->seqNum, inst->getEA());
- DPRINTF(InOrderAGEN, "[tid:%i] [sn:%i] Effective address calculated to be: "
- "%#x.\n", tid, inst->seqNum, inst->getEA());
- } else {
- panic("Unexpected memory type!\n");
- }
-
- if (fault == NoFault) {
- agen_req->done();
- } else {
- fatal("%s encountered @ [sn:%i]",fault->name(), seq_num);
- }
+ if (fault == NoFault) {
+ agen_req->done();
+ } else {
+ fatal("%s encountered while calculating address for [sn:%i]",fault->name(), seq_num);
}
} else {
DPRINTF(InOrderAGEN, "[tid:] Ignoring non-memory instruction [sn:%i].\n", tid, seq_num);
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 6fe0bcf76..5e374fa40 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -230,11 +230,10 @@ CacheUnit::execute(int slot_num)
DynInstPtr inst = cache_req->inst;
int tid;
- tid = inst->readTid();
int seq_num;
- seq_num = inst->seqNum;
- //int stage_num = cache_req->getStageNum();
+ tid = inst->readTid();
+ seq_num = inst->seqNum;
cache_req->fault = NoFault;
switch (cache_req->cmd)
@@ -304,8 +303,13 @@ CacheUnit::execute(int slot_num)
tid, name(), cache_req->inst->getMemAddr());
inst->setCurResSlot(slot_num);
- //inst->memAccess();
- inst->initiateAcc();
+
+ if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
+ inst->execute();
+ } else {
+ inst->initiateAcc();
+ }
+
break;
case CompleteReadData:
@@ -313,7 +317,10 @@ CacheUnit::execute(int slot_num)
DPRINTF(InOrderCachePort,
"[tid:%i]: [sn:%i]: Trying to Complete Data Access\n",
tid, inst->seqNum);
- if (cache_req->isMemAccComplete()) {
+
+ if (cache_req->isMemAccComplete() ||
+ inst->isDataPrefetch() ||
+ inst->isInstPrefetch()) {
cache_req->done();
} else {
DPRINTF(InOrderStall, "STALL: [tid:%i]: Data miss from %08p\n",
@@ -327,6 +334,45 @@ CacheUnit::execute(int slot_num)
}
}
+void
+CacheUnit::prefetch(DynInstPtr inst)
+{
+ warn_once("Prefetching currently unimplemented");
+
+ CacheReqPtr cache_req
+ = dynamic_cast<CacheReqPtr>(reqMap[inst->getCurResSlot()]);
+ assert(cache_req);
+
+ // Clean-Up cache resource request so
+ // other memory insts. can use them
+ cache_req->setCompleted();
+ cacheStatus = cacheAccessComplete;
+ cacheBlocked = false;
+ cache_req->setMemAccPending(false);
+ cache_req->setMemAccCompleted();
+ inst->unsetMemAddr();
+}
+
+
+void
+CacheUnit::writeHint(DynInstPtr inst)
+{
+ warn_once("Write Hints currently unimplemented");
+
+ CacheReqPtr cache_req
+ = dynamic_cast<CacheReqPtr>(reqMap[inst->getCurResSlot()]);
+ assert(cache_req);
+
+ // Clean-Up cache resource request so
+ // other memory insts. can use them
+ cache_req->setCompleted();
+ cacheStatus = cacheAccessComplete;
+ cacheBlocked = false;
+ cache_req->setMemAccPending(false);
+ cache_req->setMemAccCompleted();
+ inst->unsetMemAddr();
+}
+
Fault
CacheUnit::doDataAccess(DynInstPtr inst)
{
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index 8cd2b89cb..219329683 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -172,6 +172,10 @@ class CacheUnit : public Resource
*/
Fault doDataAccess(DynInstPtr inst);
+ void prefetch(DynInstPtr inst);
+
+ void writeHint(DynInstPtr inst);
+
uint64_t getMemData(Packet *packet);
protected:
diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc
index dbf799661..8532a30ed 100644
--- a/src/cpu/inorder/resources/tlb_unit.cc
+++ b/src/cpu/inorder/resources/tlb_unit.cc
@@ -158,8 +158,8 @@ TLBUnit::execute(int slot_idx)
if (tlb_req->fault != NoFault) {
DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "
- "addr:%08p for [sn:%i].\n", tid, tlb_req->fault->name(),
- tlb_req->memReq->getVaddr(), seq_num);
+ "addr:%08p for [sn:%i] %s.\n", tid, tlb_req->fault->name(),
+ tlb_req->memReq->getVaddr(), seq_num, inst->instName());
//insert(inst);
cpu->pipelineStage[stage_num]->setResStall(tlb_req, tid);
tlbBlocked[tid] = true;
diff --git a/src/cpu/inorder/resources/tlb_unit.hh b/src/cpu/inorder/resources/tlb_unit.hh
index b0cdac2a2..67e1bda1d 100644
--- a/src/cpu/inorder/resources/tlb_unit.hh
+++ b/src/cpu/inorder/resources/tlb_unit.hh
@@ -112,6 +112,10 @@ class TLBUnitRequest : public ResourceRequest {
flags = inst->getMemFlags();
}
+ if (req_size == 0 && (inst->isDataPrefetch() || inst->isInstPrefetch())) {
+ req_size = 8;
+ }
+
// @TODO: Add Vaddr & Paddr functions
inst->memReq = new Request(inst->readTid(), aligned_addr, req_size,
flags, inst->readPC(), res->cpu->readCpuId(), inst->readTid());
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 19:10:43 +0000