7 files changed, 12 insertions, 12 deletions

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 059996b07..5d4d3c580 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -136,7 +136,7 @@ InOrderCPU::CPUEvent::process()
         break;
 
       case Trap:
-        cpu->trapCPU(fault, tid);
+        cpu->trapCPU(fault, tid, inst);
         break;
 
       default:
@@ -649,16 +649,16 @@ InOrderCPU::updateMemPorts()
 #endif
 
 void
-InOrderCPU::trap(Fault fault, ThreadID tid, int delay)
+InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 {
     //@ Squash Pipeline during TRAP
-    scheduleCpuEvent(Trap, fault, tid, dummyInst[tid], delay);
+    scheduleCpuEvent(Trap, fault, tid, inst, delay);
 }
 
 void
-InOrderCPU::trapCPU(Fault fault, ThreadID tid)
+InOrderCPU::trapCPU(Fault fault, ThreadID tid, DynInstPtr inst)
 {
-    fault->invoke(tcBase(tid));
+    fault->invoke(tcBase(tid), inst->staticInst);
 }
 
 void 
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 450829e64..abe24d6ed 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -347,8 +347,8 @@ class InOrderCPU : public BaseCPU
     /** trap() - sets up a trap event on the cpuTraps to handle given fault.
      *  trapCPU() - Traps to handle given fault
      */
-    void trap(Fault fault, ThreadID tid, int delay = 0);
-    void trapCPU(Fault fault, ThreadID tid);
+    void trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
+    void trapCPU(Fault fault, ThreadID tid, DynInstPtr inst);
 
     /** Add Thread to Active Threads List. */
     void activateContext(ThreadID tid, int delay = 0);
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index 5486dedee..2465744e5 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -326,7 +326,7 @@ InOrderDynInst::hwrei()
 void
 InOrderDynInst::trap(Fault fault)
 {
-    this->cpu->trap(fault, this->threadNumber);
+    this->cpu->trap(fault, this->threadNumber, this);
 }
 
 
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 67ee51743..73deacb12 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -434,7 +434,7 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
 
         scheduleEvent(slot_idx, 1);
 
-        cpu->trap(cache_req->fault, tid);
+        cpu->trap(cache_req->fault, tid, inst);
     } else {
         DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated "
                 "to phys. addr:%08p.\n", tid, inst->seqNum,
diff --git a/src/cpu/inorder/resources/execution_unit.cc b/src/cpu/inorder/resources/execution_unit.cc
index 49ea329cd..91e788fbc 100644
--- a/src/cpu/inorder/resources/execution_unit.cc
+++ b/src/cpu/inorder/resources/execution_unit.cc
@@ -236,7 +236,7 @@ ExecutionUnit::execute(int slot_num)
                 } else {
                     warn("inst [sn:%i] had a %s fault",
                          seq_num, fault->name());
-                    cpu->trap(fault, tid);
+                    cpu->trap(fault, tid, inst);
                 }
             }
         }
diff --git a/src/cpu/inorder/resources/mult_div_unit.cc b/src/cpu/inorder/resources/mult_div_unit.cc
index 81e42b2b6..d9a887571 100644
--- a/src/cpu/inorder/resources/mult_div_unit.cc
+++ b/src/cpu/inorder/resources/mult_div_unit.cc
@@ -301,7 +301,7 @@ MultDivUnit::exeMulDiv(int slot_num)
                 inst->readTid(), inst->readIntResult(0));
     } else {
         warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
-        cpu->trap(fault, tid);
+        cpu->trap(fault, tid, inst);
     }    
 }
 
diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc
index 0410d6b24..59840d15b 100644
--- a/src/cpu/inorder/resources/tlb_unit.cc
+++ b/src/cpu/inorder/resources/tlb_unit.cc
@@ -176,7 +176,7 @@ TLBUnit::execute(int slot_idx)
                     scheduleEvent(slot_idx, 1);
 
                     // Let CPU handle the fault
-                    cpu->trap(tlb_req->fault, tid);
+                    cpu->trap(tlb_req->fault, tid, inst);
                 }
             } else {
                 DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated "