1 files changed, 9 insertions, 10 deletions
diff --git a/src/cpu/kvm/X86KvmCPU.py b/src/cpu/kvm/X86KvmCPU.py
index 18a4d3d6f..411db7dbe 100644
--- a/src/cpu/kvm/X86KvmCPU.py
+++ b/src/cpu/kvm/X86KvmCPU.py
@@ -27,21 +27,20 @@
 # Authors: Andreas Sandberg
 
 from m5.params import *
+from m5.SimObject import *
 from BaseKvmCPU import BaseKvmCPU
 
 class X86KvmCPU(BaseKvmCPU):
     type = 'X86KvmCPU'
     cxx_header = "cpu/kvm/x86_cpu.hh"
 
-    @classmethod
-    def export_methods(cls, code):
-        code('''
-      void dumpFpuRegs();
-      void dumpIntRegs();
-      void dumpSpecRegs();
-      void dumpXCRs();
-      void dumpXSave();
-      void dumpVCpuEvents();
-''')
+    cxx_exports = [
+        PyBindMethod("dumpFpuRegs"),
+        PyBindMethod("dumpIntRegs"),
+        PyBindMethod("dumpSpecRegs"),
+        PyBindMethod("dumpXCRs"),
+        PyBindMethod("dumpXSave"),
+        PyBindMethod("dumpVCpuEvents"),
+    ]
 
     useXSave = Param.Bool(True, "Use XSave to synchronize FPU/SIMD registers")