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-rw-r--r--src/cpu/memtest/memtest.hh96
1 files changed, 64 insertions, 32 deletions
diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index 42fb235db..a0e58126b 100644
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -35,25 +35,26 @@
#include <set>
#include "base/statistics.hh"
-#include "mem/functional/functional.hh"
-#include "mem/mem_interface.hh"
+//#include "mem/functional/functional.hh"
+//#include "mem/mem_interface.hh"
#include "sim/eventq.hh"
#include "sim/sim_exit.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
+class PhysicalMemory;
class ThreadContext;
-class MemTest : public SimObject
+class MemTest : public MemObject
{
public:
MemTest(const std::string &name,
- MemInterface *_cache_interface,
- FunctionalMemory *main_mem,
- FunctionalMemory *check_mem,
+// MemInterface *_cache_interface,
+ PhysicalMemory *main_mem,
+ PhysicalMemory *check_mem,
unsigned _memorySize,
unsigned _percentReads,
- unsigned _percentCopies,
+// unsigned _percentCopies,
unsigned _percentUncacheable,
unsigned _progressInterval,
unsigned _percentSourceUnaligned,
@@ -61,6 +62,8 @@ class MemTest : public SimObject
Addr _traceAddr,
Counter _max_loads);
+ virtual void init();
+
// register statistics
virtual void regStats();
@@ -69,6 +72,8 @@ class MemTest : public SimObject
// main simulation loop (one cycle)
void tick();
+ virtual Port *getPort(const std::string &if_name, int idx = -1);
+
protected:
class TickEvent : public Event
{
@@ -82,16 +87,61 @@ class MemTest : public SimObject
};
TickEvent tickEvent;
+ class CpuPort : public Port
+ {
+
+ MemTest *memtest;
+
+ public:
+
+ CpuPort(const std::string &_name, MemTest *_memtest)
+ : Port(_name), memtest(_memtest)
+ { }
+
+ protected:
+
+ virtual bool recvTiming(Packet *pkt);
+
+ virtual Tick recvAtomic(Packet *pkt);
+
+ virtual void recvFunctional(Packet *pkt);
+
+ virtual void recvStatusChange(Status status);
+
+ virtual void recvRetry();
+
+ virtual void getDeviceAddressRanges(AddrRangeList &resp,
+ AddrRangeList &snoop)
+ { resp.clear(); snoop.clear(); }
+ };
+
+ CpuPort cachePort;
+
+ class MemTestSenderState : public Packet::SenderState
+ {
+ public:
+ /** Constructor. */
+ MemTestSenderState(uint8_t *_data)
+ : data(_data)
+ { }
- MemInterface *cacheInterface;
- FunctionalMemory *mainMem;
- FunctionalMemory *checkMem;
+ // Hold onto data pointer
+ uint8_t *data;
+ };
+
+// Request *dataReq;
+ Packet *retryPkt;
+// MemInterface *cacheInterface;
+ PhysicalMemory *mainMem;
+ PhysicalMemory *checkMem;
SimpleThread *thread;
+ bool accessRetry;
+
unsigned size; // size of testing memory region
unsigned percentReads; // target percentage of read accesses
- unsigned percentCopies; // target percentage of copy accesses
+// unsigned percentCopies; // target percentage of copy accesses
unsigned percentUncacheable;
int id;
@@ -128,29 +178,11 @@ class MemTest : public SimObject
Stats::Scalar<> numCopiesStat;
// called by MemCompleteEvent::process()
- void completeRequest(MemReqPtr &req, uint8_t *data);
+ void completeRequest(Packet *pkt);
- friend class MemCompleteEvent;
-};
+ void doRetry();
-
-class MemCompleteEvent : public Event
-{
- MemReqPtr req;
- uint8_t *data;
- MemTest *tester;
-
- public:
-
- MemCompleteEvent(MemReqPtr &_req, uint8_t *_data, MemTest *_tester)
- : Event(&mainEventQueue),
- req(_req), data(_data), tester(_tester)
- {
- }
-
- void process();
-
- virtual const char *description();
+ friend class MemCompleteEvent;
};
#endif // __CPU_MEMTEST_MEMTEST_HH__