diff options
Diffstat (limited to 'src/cpu/minor/lsq.hh')
| -rw-r--r-- | src/cpu/minor/lsq.hh | 23 |
1 files changed, 14 insertions, 9 deletions
diff --git a/src/cpu/minor/lsq.hh b/src/cpu/minor/lsq.hh index 23b47c53c..a7c7cb632 100644 --- a/src/cpu/minor/lsq.hh +++ b/src/cpu/minor/lsq.hh @@ -145,9 +145,6 @@ class LSQ : public Named /** The underlying request of this LSQRequest */ RequestPtr request; - /** Fault generated performing this request */ - Fault fault; - /** Res from pushRequest */ uint64_t *res; @@ -160,6 +157,9 @@ class LSQ : public Named * that's visited the memory system */ bool issuedToMemory; + /** Address translation is delayed due to table walk */ + bool isTranslationDelayed; + enum LSQRequestState { NotIssued, /* Newly created */ @@ -186,9 +186,14 @@ class LSQ : public Named protected: /** BaseTLB::Translation interface */ - void markDelayed() { } + void markDelayed() { isTranslationDelayed = true; } + + /** Instructions may want to suppress translation faults (e.g. + * non-faulting vector loads).*/ + void tryToSuppressFault(); void disableMemAccess(); + void completeDisabledMemAccess(); public: LSQRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_, @@ -701,11 +706,11 @@ class LSQ : public Named /** Single interface for readMem/writeMem/amoMem to issue requests into * the LSQ */ - void pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, - unsigned int size, Addr addr, Request::Flags flags, - uint64_t *res, AtomicOpFunctor *amo_op, - const std::vector<bool>& byteEnable = - std::vector<bool>()); + Fault pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, + unsigned int size, Addr addr, Request::Flags flags, + uint64_t *res, AtomicOpFunctor *amo_op, + const std::vector<bool>& byteEnable = + std::vector<bool>()); /** Push a predicate failed-representing request into the queues just * to maintain commit order */ |