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diff --git a/src/cpu/minor/stats.cc b/src/cpu/minor/stats.cc
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+/*
+ * Copyright (c) 2012-2014 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andrew Bardsley
+ */
+
+#include "cpu/minor/stats.hh"
+
+namespace Minor
+{
+
+MinorStats::MinorStats()
+{ }
+
+void
+MinorStats::regStats(const std::string &name, BaseCPU &baseCpu)
+{
+    numInsts
+        .name(name + ".committedInsts")
+        .desc("Number of instructions committed");
+
+    numOps
+        .name(name + ".committedOps")
+        .desc("Number of ops (including micro ops) committed");
+
+    numDiscardedOps
+        .name(name + ".discardedOps")
+        .desc("Number of ops (including micro ops) which were discarded "
+            "before commit");
+
+    numFetchSuspends
+        .name(name + ".numFetchSuspends")
+        .desc("Number of times Execute suspended instruction fetching");
+
+    quiesceCycles
+        .name(name + ".quiesceCycles")
+        .desc("Total number of cycles that CPU has spent quiesced or waiting "
+              "for an interrupt")
+        .prereq(quiesceCycles);
+
+    cpi
+        .name(name + ".cpi")
+        .desc("CPI: cycles per instruction")
+        .precision(6);
+    cpi = baseCpu.numCycles / numInsts;
+
+    ipc
+        .name(name + ".ipc")
+        .desc("IPC: instructions per cycle")
+        .precision(6);
+    ipc = numInsts / baseCpu.numCycles;
+}
+
+};